A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2025 | VOLUME 27 | ISSUE 1 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org BACKSIDE DELAYERING OF 10 nm NODE ICs QUANTUM DIAMOND MICROSCOPY FOR FAILURE ANALYSIS HIGHLIGHTS FROM ISTFA 2024 LOW FREQUENCY NOISE SPECTROSCOPY 3 18 8 28
A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2025 | VOLUME 27 | ISSUE 1 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org BACKSIDE DELAYERING OF 10 nm NODE ICs QUANTUM DIAMOND MICROSCOPY FOR FAILURE ANALYSIS HIGHLIGHTS FROM ISTFA 2024 LOW FREQUENCY NOISE SPECTROSCOPY 3 18 8 28
edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 ABOUT THE COVER The image shows a transistor with the bond wires nearly fusing during failure simulation. The failure simulation was performed to approximate the electrical overstress (over current) event the original failed transistor experienced. Photo by Ryan Winkler, Hi-Rel Laboratories Inc., First Place Winner in Color Images, 2024 EDFAS Photo Contest. A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS FEBRUARY 2025 | VOLUME 27 | ISSUE 1 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Low Frequency Noise Spectroscopy: A Powerful Diagnostic Tool for Trap Identification in Active and Passive Components B. Cretu, A. Tahiat, R. Coq Germanicus, F. Bezerra, C. Bunel, A. Veloso, and E. Simoen This article describes and shows application of low frequency noise spectroscopy to identify stable traps induced by proton irradiations on silicon passive devices. Author Guidelines Author guidelines and a sample article are available at edfas. org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 3 8 2 GUEST EDITORIAL E. Jan Vardaman 32 WEFA 2024 ISTFA SESSION WRAP 33 ISTFA PANEL & USER GROUP SUMMARY 40 2024 EDFAS AWARD WINNERS 41 2025 EDFAS AWARDS 42 CALL FOR NOMINATIONS Felix Beaudoin 43 BOARD OF DIRECTORS NEWS Chris Richardson 44 FIB SEM SUMMARY Michael DiBattista 45 DIRECTORY OF FA LABS Rosalinda Ring 46 EDUCATION NEWS Navid Asadi 47 LITERATURE REVIEW Michael R. Bruce 48 PRODUCT NEWS Ted Kolasa 50 TRAINING CALENDAR Rosalinda Ring 52 ADVERTISERS INDEX Quantum Diamond Microscopy for Semiconductor Failure Analysis Marwa Garsi, Andreas Welscher, Manuel Schrimpf, Bartu Bisgin, Michael Hanke, Horst Gieser, Daniela Zahn, and Fleming Bruckmaier Quantum diamond microscopy is presented as a nondestructive, innovative tool, and case studies compare it with existing electrical failure analysis techniques. 18 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Full Chip Backside Delayering of 10 nm Node Integrated Circuits with Chemically Assisted Focused Ion Beam Deprocessing Michael DiBattista, Robert Chivas, Ata Tafazoli Yazdi, Jonathan Sheeder, and Scott Silverman The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer starting from the shallow trench isolation layer, enabling highresolution SEM imaging at each layer. 8 3 ISTFA 2024 Highlights A recap of the ISTFA 2024 event includes General Chair Yan Li’s wrap-up as well as a list of the winning ISTFA papers and posters. 28 28 18
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 2 Governments around the world are investing in their domestic semiconductor industries, and in some cases the ecosystem for packaging and assembly. The U.S. CHIPS and Science Act includes $52 billion in subsidies for domestic semiconductor research and manufacturing. An investment tax credit of 25% is offered for investments in semiconductor manufacturing and processing equipment. The purpose of the act is to: • Increase capacity in domestic manufacturing and emerging technologies (i.e., onshore semiconductor manufacturing) • Promote critical supply chain resilience • Strengthen the national capacity for manufacturing innovation, and expand workforce development efforts • Deliver important measurement and technology to semiconductor R&D needs U.S. CHIPS ACT FUNDING Much of the funding is targeted for semiconductor fabrication, but some is focused on the packaging and assembly. The U.S. Department of Commerce (DOC) will manage and support industry at large. The $39 billion incentive program provides direct funds as grants or loans to increase capacity. New advanced semiconductor node fabs have received the most attention, but legacy fabs and packaging will also be funded. Under the program, $39 billion in incentives has been allocated to invest in U.S. production of strategically important semiconductor chips, to assure a sufficient sustainable and secure supply of older- and current-generation chips for national security purposes and for critical manufacturing industries. There is an allocation of $11 billion to strengthen U.S. semiconductor R&D leadership to catalyze and capture the next set of critical technologies, applications, and industries. Funding of $2 billion for Department of Defense (DOD) Microelectronics Commons is targeted to establish a national network that will create direct pathways to commercialization for U.S. microelectronics researchers and designers from “lab to fab.” Workforce development initiatives underpin all programs. The National Advanced Packaging Manufacturing Program (NAPMP) has been allocated $2.5 billion. The focus is to strengthen semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem. The NAPMP will make R&D investments that leverage existing areas of FEBRUARY 2025 | VOLUME 27 | ISSUE 1 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL ELECTRONICS INDUSTRY GETS GOVERNMENT ATTENTION E. Jan Vardaman, TechSearch International Inc. jan@techsearchinc.com edfas.org (continued on page 25) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/KLA nicholas.antoniou@kla.com Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Jason Holm NIST Ted Kolasa Northrop Grumman Space Systems Joy Liao Nvidia Corp. Rosalinda M. Ring NenoVision Tom Schamp E-Space David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2025 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Vardaman
edfas.org 3 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 EDFAAO (2025) 1:3-7 1537-0755/$19.00 ©ASM International® FULL CHIP BACKSIDE DELAYERING OF 10 nm NODE INTEGRATED CIRCUITS WITH CHEMICALLY ASSISTED FOCUSED ION BEAM DEPROCESSING Michael DiBattista1, Robert Chivas2, Ata Tafazoli Yazdi1, Jonathan Sheeder1, and Scott Silverman1 1Varioscale, San Marcos, California 2L3Harris, Carlsbad, California miked@varioscale.com INTRODUCTION Physical delayering of semiconductor devices is a critical step for extracting the structure of the internal features used to verify and validate the integrated circuit (IC) design and layout.[1] Delayering techniques allow for the visualization of the lower layers of the IC using microscopy in subsequent steps. This process is essential for security, intellectual property (IP) investigations, and verification and validation activities.[2] The high-level approach is to remove layers of the IC individually, image the device in a scanning electron microscope (SEM), stitch the individual layers together, and then extract information.[3] As the technology manufacturing node has advanced, the corresponding transistor and interconnect layers shrink, resulting in ion-based techniques arising to deal with increased challenges.[4] The features of interest are often too small with too many interconnect layers to be analyzed with optical microscopy or x-ray techniques. Full chip delayering of integrated circuits has been identified as a significant challenge on the Electronic Device Failure Analysis Society (EDFAS) Failure Analysis Roadmap.[5] Advanced manufacturing node devices, particularly those at 10 nm and smaller, present unique challenges due to the nanometer scale of the structures and the layer thickness. BACKGROUND A successful method for large scale full chip delayering of 10 nm ICs is to approach the task from the substrate side of the device.[6] In addition to enabling the visualization of the transistor structure very early in the deprocessing work flow, this also enables examination of the n-well dopant layers with SEM voltage contrast (VC) before the interconnect delayering process starts.[7] Identifying the locations of the n-well and p-well dopant positions helps to distinguish the transistor type and the power (Vdd/Vcc) and ground (GND) interconnect signals that lie deeper in the chip. The substrate side approach also provides significant advantages at 10 nm; the interconnect layers are extremely thin and uniform, reducing some of the more challenging aspects and required time for ion beam milling with chemistry. The process for advanced node delayering begins with precision mechanical thinning of the silicon substrate to below 5 microns of remaining silicon thickness (RST).[8] After the device substrate is thinned, SEM VC inspection is followed by rapid substrate removal with xenon difluoride (XeF2) to the shallow trench isolation (STI) layer. The XeF2 process will stop elegantly on the shallow trench isolation, but the active FinFET transistors will be etched away leaving remaining STI structures intact.[9] This work, featured in this article, takes advantage of chemically assisted argon ion focused ion beam (FIB) processing with ultraviolet (UV) spectroscopy endpointing to destructively delayer starting from the STI layer. This enables follow-on high-resolution SEM imaging at Fig. 1 A chamber view of the argon ion sputtering system, showing the optical view port for UV photon collection, the argon ion source, the gas dosing effuser, and the stage for sample positioning.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 4 each layer with a ZEISS mSEM. The mSEM microscope is a multi-electron beam tool allowing high speed imaging of large areas of the delayered device.[10] METHODOLOGY The process begins with a vacuum chamber equipped with a two-lens post deflection argon ion source that operates up to 5 KeV as shown in Fig. 1. The subsequent introduction of water vapor on the sample surface facilitates the uniform delayering process, overcoming the challenges associated with traditional ion sputter delayering methods of heterogenous surfaces like copper and silicon oxide. The water effectively adsorbs on the surface and slows the individual material sputter rates so they are equalized. The water dosing involves hardware improvements over traditional FIB gas injection to efficiently deliver the chemistry uniformly over large sample areas and has advantages as shown in Fig. 2. The addition of a large effuser element helps to improve the efficiency of the water delivery to the sample surface over simply injecting gas chemistry.[11] Delayering quality is controlled by several factors including effective chemical delivery, ion beam shape, ion current density, and charge mitigation. The argon ion beam spot size for full chip delayer is on the order of 200 μm diameter. Reaching the next layer of the 10 nm device is the Metal 0 (M0) interconnect layer. It is constructed of a dense tungsten routing structure. The high atomic number of tungsten (W) makes stopping on the layer very effective with water dosing and Ar+ milling. The W material has multiple primary UV intensity peaks that are easily measured.[12] In combination with uniform delayering, dual photomultiplier tubes (PMTs) as photon detectors are used to collect the UV photons from the silicon oxide (SiO2) at the 250 nm wavelength and the metal layers (Cu and W) at 325 nm as shown in Fig. 3.[13] Aluminum interconnects can also be monitored by measuring a strong UV emission peak at the 395 nm wavelength as shown in Fig. 4. RESULTS Figure 5 shows a 64 μm x 50 μm selected area image capture of the 10 nm IC surface at the M0 layer using the Fig. 2 A schematic demonstrating the design of the gas doser system with an effuser (Pe) in comparison to a traditional gas injector in a FIB system. The effuser results in a more efficient delivery to the sample and results in a lower background chamber pressure. Fig. 3 UV plots to monitor the sputter rates of the silicon oxide and metal interconnect showing the silicon peak first as the STI layer is removed and the emergence of the tungsten V0 layer. These plots are generated by two separate PMT detectors with narrow bandwidth filters at 250 nm for silicon, and 325 nm for copper/tungsten. Fig. 4 An ion induced UV spectrum from Ar+ sputtered aluminum surface showing two peaks with the primary peak at the 395 nm wavelength.
edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 mSEM and custom capture software. The low magnification stitched image of the high-level structure of blocks shows a large memory location with surrounding logic transistors. Zooming further into the memory block section, the individual tungsten structures are clearly observed in Fig. 6. The memory locations are useful benchmarks for Fig. 5 A stitched scanning electron microscope (SEM) image of the chemically deprocessed integrated circuit at the Metal 0 (M0) layer. The field of view is approximately 64 μm x 50 μm. Fig. 6 A zoomed image of the tungsten M0 layer in the memory block of the 10 nm device. The resolution of the ZEISS mSEM is sufficient to resolve the individual features of the tungsten vias in the memory cells. Fig. 7 A corresponding zoomed image of the copper Via 0 (V0) and the copper Metal 1 (M1) layer that lie under the M0 layer after removal with chemically assisted argon ion sputtering. The image quality allows for stitching and stacking of the layers. the delayering quality because the architecture of the unit cell is easily determined. The mSEM image quality and resolution is challenged with the feature size of 10 nm devices, but it is sufficient to clearly make out individual vias and spacing. Subsequent delayering to the next layer with water assistance and endpointing with UV spectroscopy allows the acquisition of the Via 0 (V0) and Metal 1 (M1) image layer as shown in Fig. 7. The copper M1 horizontal lines and the copper vias are clearly seen. These features are sufficiently delineated such that they can be stacked with the previous M0 layer to begin the layout reconstruction process. After the M1 layer, the process can be repeated through the interconnect stack. Figure 8 shows the Metal 2 layer in the same memory location. The metal interconnect lines are intact but do show contrast differences across the lines that make algorithm-based structure extraction difficult if not impossible.[14] Artificial intelligence-based methods have shown to have much more promise in the initial attempts in the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program. DISCUSSION Chemically assisted scanning Ar+ beam delayering with UV photon-based endpoint detection is a highly successfully method to physically delayer 10 nm ICs across the full chip and areas across the device that delayer slower than their surroundings are observed. This is often due to the circuit architecture. For example, in the logic area, design features like decoupling capacitors are meant to store electrical charge and have demonstrated different sputter rates. This results in remaining material from the layer above while the surrounding areas are cleanly removed as shown in Fig. 9. To remedy this situation in the future, we have incorporated an electron flood gun to balance the accumulated charge in these structures. Delivering a flood of electrons creates an equal potential charge surface that will enable these device structures to interact with the 5 KeV ion beam the same as their surroundings. CONCLUSION Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The challenges associated with advanced node devices,
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 6 particularly those at 10 nm and smaller, require innovative and precise delayering techniques. Argon ion milling from the substrate side using water-assisted etching can achieve nanometer uniformity over the full chip and use UV spectroscopy techniques to determine when to stop on the via or metal interconnect layer. Interconnect layers constructed of copper or aluminum can be analyzed, as well as memory and logic locations. In-chip features designed to store electron charge delayer at an even slower rate as shown, but the authors believe the next steps of involving an electron flood gun will mitigate the positive charge accumulation and allow the sputter rate to normalize across those features. ACKNOWLEDGMENTS Substantial amounts of this work rely on research performed during the Intelligence Advanced Research Project Agency (IARPA) funded project for the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN). This project focused on the full analysis of 10 nm integrated circuits using a newly developed scanning argon ion tool, a ZEISS mSEM, and custom developed software for image acquisition and stitching. REFERENCES 1. N. Kovač: “Homogenous Delayering: A Key Challenge for Successful Reverse Engineering,” Fraunhofer Research Institute for Microsystems and Solid State Technologies EMFT, HARRIS Workshop @ Bochum, January 24-25, 2023. 2. A.G. Kimura, et al.: “Applied Failure Analysis Tools and Techniques Toward Integrated Circuit Trust and Assurance,” EDFA, February 2021, 23(1), p. 12-18, doi.org/10.31399/asm.edfa.2021-1.p012. 3. D. Douglass and K. Godin: “Whole-Chip Delayering for Failure Analysis and Quality Assurance,” EDFA, May 2023, 25(2), p. 4-8, doi. org/10.31399/asm.edfa.2023-2.p004. 4. P. Nowakowski, et al.: “An Innovative Technique for Large-scale Delayering of Semiconductor Devices with Nanometric-scale Surface Flatness,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2022, doi. org/10.31399/asm.cp.istfa2022p0414. 5. N. Antoniou and B. Foran: “The EDFAS FA Technology Roadmap—FA Future Roadmap,” EDFA, May 2023, 25(2), p. 44-46, doi.org/10.31399/ asm.edfa.2023-2.p044. 6. E.L. Principe, et al.: “Steps Toward Automated Deprocessing of Integrated Circuits,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2017, p. 285-298, doi.org/10.31399/asm.cp.istfa2017p0285. 7. L. Li-Lung, H. Gao, and H. Xiao: “Surface Effect on SEM Voltage Contrast and Dopant Contrast,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2009, p. 202-207, doi.org/10.31399/asm.cp.istfa2009p0202. 8. C.C. Tsao, et al.: “Reliability of Ultra Thinning of Flip Chips for Through-silicon Analyses,” Proc. IEEE International Reliability Physics Symposium, 2002, p. 198-204, doi.org/10.1109/RELPHY.2002.996636. 9. D. Xia, et al.: “Enhancement of XeF2-assisted Gallium Ion Beam Etching of Silicon Layer and Endpoint Detection from Backside in Circuit Editing,” J. Vac. Sci. Technol. B, 2015, 33, 06F501, doi. org/10.1116/1.4928744. 10. D. Zhang, et al.: “Fast, Full Chip Image Stitching of Nanoscale Integrated Circuits,” 2019. 11. A.W. Czanderna, C.J. Powell, and T.E. Madey: “Specimen Handling, Preparation, and Treatments in Surface Characterization,” Methods of Surface Characterization, Volume 4, Kluwer Academic/Plenum Publishers, New York 1998. 12. N.H. Tolk, et al.: “Photon Emission from Low-energy Ion and Neutral Bombardment of Solids,” Radiation Effects, 1973, 18(3-4), p. 221-229, doi.org/10.1080/00337577308232126. Fig. 8 The corresponding zoomed Metal 2 (M2) layer in the memory block showing cleaning exposed metal interconnects with contrast differences on individual signal lines. Fig. 9 A high resolution multiSEM capture from the logic area showing V0 structures and remnants of the FinFET gates in the decoupling capacitors of the chip. ABOUT THE AUTHORS Michael DiBattista is the vice president at Varioscale Inc. He is currently focused on large scale de- processing on advanced node semiconductor devices and laser and chemical-based solutions for 3D heterogeneous integrated microsystem failure analysis. He has worked in the semiconductor industry for 24 years, holding positions at Intel Corp., FEI Company (ThermoFisher), and Qualcomm Inc. focused on developing tools and technology to support semiconductor physical failure analysis and focused ion beam-based circuit modification. DiBattista has more than 30 publications in the semiconductor, electron/ion microscopy, and chemical sensor fields and has 12 issued patents. He received his Ph.D., M.S.E., and B.S.E. in chemical engineering from the University of Michigan.
edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 Robert Chivas is currently a research scientist at L3Harris. His previous work at Varioscale helped pioneer the true 5-Axis Adaptive CNC Mill for grinding and polishing integrated circuits. Over that time, he has gained extensive experience preparing integrated circuits and packages of all types for semiconductor failure analysis and FIB based circuit edit. Chivas also has broad experience in the fields of semiconductor materials, photonics, optics, and fiber optics. He has published more than 11 papers and one patent covering sample preparation, photonics, and nanotechnology. Ata Tafazoli Yazdi is the lead software engineer at Varioscale Inc. He is currently focused on developing software for failure analysis tools targeting multi-die integrated microsystems. He received his B.S. in computer science from the University of California, San Diego in 2020. Jonathan Sheeder is the production manager at Varioscale Inc. He is responsible for engineering development, production, and product support across the full range of Varioscale systems. He previously worked at General Atomics in San Diego as a research and development engineer across several projects including bioreactor fuels and ceramic composites for nuclear energy applications. He graduated from the University of California, San Diego with a degree in chemical engineering. Scott Silverman, president and founder of Varioscale, earned his BSEE from Rensselaer Polytechnic Institute. Silverman has extensive experience in the design, development, and commercialization of semiconductor capital equipment. He was the principal investigator (PI) for the IARPA funded Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) project for the Varioscale team. He was also the PI for the IARPA Circuit Analysis Tool (CAT) project that developed backside sample preparation tools.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 8 LOW FREQUENCY NOISE SPECTROSCOPY: A POWERFUL DIAGNOSTIC TOOL FOR TRAP IDENTIFICATION IN ACTIVE AND PASSIVE COMPONENTS B. Cretu1, A. Tahiat1, R. Coq Germanicus1, F. Bezerra2, C. Bunel3, A. Veloso4, and E. Simoen5 1Normandie Université, Caen, France 2Centre National d’Etudes Spatiales, Toulouse, France 3Murata Integrated Passive Solutions, Caen, France 4Imec Kapeldreef, Leuven, Belgium 5Ghent University, Gent, Belgium bogdan.cretu@ensicaen.fr EDFAAO (2025) 1:8-17 1537-0755/$19.00 ©ASM International® INTRODUCTION An essential aspect of evaluating the quality of materials and the device reliability is the use of fast, nondestructive, and accurate electrical characterization techniques that allow for the determination of key electrical parameters. Because of its sensitivity to defects and imperfections in the current path, low frequency noise has been employed as an efficient tool to assess device quality or reliability from both application and process optimization perspectives.[1-9] Low frequency noise studies are used to predict circuit performance, to obtain information on the charge transport mechanisms in devices, and to quantify device performances. Studying the generation-recombination (GR) noise as a function of the temperature gives information on the processing-induced defects in advanced MOSFET devices, identifying deep-level traps located in the gate stack or in the semiconductor material irrespective of the architecture and geometrical dimensions of the devices.[10-13] This diagnostic tool is more interesting as the low frequency noise related to free carrier trapping/ de-trapping phenomena increases with the decrease of the active surface of the components unlike other electrical characterization techniques for trap identification, e.g., the conventional deep level transient spectroscopy (DLTS) technique.[14] The methodology to estimate the noise parameters when one or several Lorentzian noise contributions appear in the total noise is described in references 10 and 15. The low frequency noise spectroscopy theory and methodology key points for traps located in the depletion zone are detailed in references 10 to 12. The work in this article focuses on traps located in the depleted region of the semiconductor material of already studied nanoscale transistor technologies. Technological and geometrical dimensions of the different architectures and typical low frequency noise spectra may be found in references 16 to 19 for ultra-thin buried oxide (UTBOX) transistors on silicon on insulator (SOI) substrates, in reference 15 for Si/SiGe superlattice I/O n-channel FinFETs, in reference 20 for gate all around (GAA) nanowires (NW), and reference 21 describes GAA vertically stacked lateral nanosheet (NS) FETs. An example is also given of a successful application of the low frequency noise spectroscopy to identify stable traps induced by proton irradiations on silicon passive devices.[22] THEORY AND METHODOLOGY The low frequency noise may contain flicker noise, white noise, and Lorentzian noise contribution. The generation-recombination (GR) noise corresponds to a Lorentzian spectrum, which is described by the expression:[10] (Eq 1) and is characterized by a corner frequency, f0, (or a char- acteristic time constant defined as τ0 = 1⁄((2πf0)) and by a plateau S0 that may be observed for frequencies f << f0. Considering uncorrelated noise sources and that the white noise level is Wn, the flicker noise level, Kf , at a frequency
edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 of 1 Hz, and each GR noise contribution is described by Eq 1, the input-referred power spectral density may be written as:[23] (Eq 2) In order to estimate the noise parameters, it is suggested to use the behavior of the input-referred noise multiplied by the frequency versus the frequency. In this representation, the flicker noise will exhibit a plateau giving the Kf level, and the slope of the linear increase of the Sv(f ) . f with the frequency in the highest frequency range may give the white noise level Wn. If only one GR noise contribution is present, a bump centered at the characteristic frequency will appear. As the “bump” takes place at the characteristic frequency, f0, this allows for an easy determination of f0. The plateau of the Lorentzian S0, if the white noise level may be neglected around f0 is given by:[10,15] (Eq 3) As shown in Fig. 1, the noise spectra may be perfectly represented using the model of Eq 2. A methodology to estimate the noise parameters if more than one Lorentzian contributes to the total noise is given in reference 15, where the first step is estimating the characteristic frequency and the plateau corresponding to the higher level of GR contribution. The traps located in the depleted region of the semiconductor material are characterized by a discrete and unique deep energy level, ET. The GR noise will arise when the Fermi level crosses the trap level in the semiconductor bandgap. If the applied device polarization changes, the Fermi level changes. However, as long as a crossing point exists between the Fermi and the trap level, the same trap will be probed. Considering the Shockley-Read-Hall (SRH) model, the characteristic time constant will be given by the τ0 -1 = c n nt (or cp pt), [10,13] where c n = σnvth and cp = σpvth are the capture rates for electrons and holes, σn and σp are the electron and hole capture cross sections, vth is the thermal velocity; nt and pt being the carrier concentration when the quasiFermi level crosses the trap with energy ET. Consequently, the characteristic time constant, τ0, or the corresponding corner frequency, f0, is independent on the applied device polarisation at a fixed operation temperature.[10-12] In a general way, the evolution of the characteristic relaxation time of GR noise contribution at a fixed temperature as a function of the applied gate bias makes it possible to locate the trap.[10-12] Typical examples are given in Fig. 2. The variation of the characteristic time constant with temperature at fixed polarization may allow for the identification of the energy difference between the appropriate band energy and the trap energy and the capture cross section of the trap through the Arrhenius plot, which may be constructed using:[10-12] (Eq 4) where kB is the Boltzmann constant, T is the temperature, h is the Planck constant, me* and mh * are the effective mass of electrons and holes, respectively, and Mc is the number of conduction band energy minima. Equation 4 is valid for n-channel devices. The physical nature of these traps can be found by comparing the energy and capture cross section of the identified traps with data in the literature. An example of the evolution of the normalized voltage noise spectral density multiplied by frequency at fixed Fig. 1 Typical noise measurement and model using Eq 2: flicker noise, white noise, and 1 GR noise contribution are considered to obtain the best agreement between measurement and model. Device: standard UTBOX, equivalent oxide thickness (EOT) of 2.1 nm, thickness of the buried oxide (TBOX) of 15 nm, thickness of the silicon film (TSi) of 16 nm, ratio between the channel gate length and width (LG / WG) of 1 µm / 1µm, operated at a drain current polarization (ID) of 1 µA (for an applied drain to source voltage (VDS) of 50 mV) and at a temperature of 230 K. [16] Estimated noise parameters: Wn = 3.5∙10-14 V2⁄Hz, Kf = 2.6∙10-10 V2, S 0 = 5∙10-10 V2⁄Hz, f0 = 3Hz.
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 10 drain current polarization of 1 µA is shown in Fig. 3. The evolution of the GR noise parameters with the temperature allows construction of Arrhenius plots (as shown in Figs. 4a and 5a) and an estimation from the slope of the evolution of ln(τ0T2) versus 1 ⁄ (k BT ) of the energy difference between the appropriate band energy and the trap energy (ΔE) and from the intercept of this evolution the free carrier capture cross section of the trap. In linear operation, the Lorentzian plateau S0 of the GR noise resulting from traps situated in the depletion region of the transistor may be expressed as:[10-12] (Eq 5) where q is the absolute electron charge, W and L are the effective channel width and length, Cox is the gate capacitance per unit of area, Neff is the surface trap density, NT is the volume trap density, Wd is the silicon depletion depth, and B is a coefficient estimated to be equal to 1/3.[10] As the nanoscaled devices are fully depleted, the silicon depletion depth Wd is taken as half of the fin width (Wfin/2) for FinFET devices, as the Si film thickness (TSi ) for UTBOXs and as half of the nanowire width (WNW/2) for GAA NW FETs. The volume trap density may also be estimated employing the following expression:[10] (Eq 6) However, disagreement between the obtained values of the volume trap densities using Equations 5 and 6 was described in reference 24. This may be related to the theoretical value of the B coefficient, which is evaluated for planar devices with one gate, and to the Wd value as it comes from geometrical consideration as the devices are already fully depleted. It may be suggested that the methods used to estimate the volume trap densities are no longer accurate. Consequently, even if the traps situated in the depletion region are related to a volume phenomenon, as the linear evolution between the plateau and the characteristic frequency of the GR noise contribution gives without any additional assumption the value of the surface trap density, the latter one should be used as a figure of merit when comparing different technologies and architectures. Equation 5 clearly indicates that a linear dependency between the plateau S0 and the characteristic relaxation time constant τ0 of the GR noise should exist. As a consequence, Fig. 2 Example of estimated relaxation time constant of GR contributions as a function of the applied gate voltage (VGS) at 300 K. Device: n channel GAA NW FET, EOT of 5.6 nm, LG / WG = 250 nm / 160 nm, VDS = 50 mV, T = 300 K.[18] The β coefficient of the exponential behavior of the τ 0 with the applied gate voltage (τ0~eβV GS) may give indication of the trap location: for the circle symbols β of -32 V-1 suggests that the traps are located at the Si/dielectric interface;[10] for the triangle and diamond symbols β of -3.5 V-1 and of -3.7 V-1 suggests traps located in the depleted Si film near the Si/dielectric interface,[10,12] and for the square symbols as β of 0 V-1 the traps are located in the depleted Si film.[10] Fig. 3 Typical input-referred voltage power spectrum noise multiplied by the frequency as a function of temperature for the same devices as in Fig. 1.
edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 the S0 versus τ0 plot may additionally be used to confirm that it is about the same trap over the entire investigated temperature range. Examples of S0 versus τ0 are plotted in Figs. 4b and 5b. In Fig. 6 Sv,GR(f0,T)f0 versus the temperature is given for the trap identified in Fig. 5, permitting an estimate of the trap volume density. IDENTIFIED TRAPS IN ACTIVE DEVICES Table 1 summarizes the main identified traps in different 16 nm and below state-of-the-art MOSFET devices in the temperature range of 80 K to 340 K. The main differences between UTBOX technologies are related to the gate stack and the resulting equivalent oxide thickness (EOT), 2.6 nm, 2.1 nm, and 1.9 nm, respectively.[16-18] The standard UTBOX have the channel orientation <100> while for the rotated UTBOX the channel orientation is <110>. In reference 19 the resulting EOT is also 2.6 nm, but the gate stack consists of 2.5 nm SiON on top of 1 nm interfacial SiO2 instead of 2.5 nm HfSiO with 60% Hf +1.5 nm SiO2, as recorded in reference 16. The nature of the traps is generally established by using results from the standard DLTS analysis.[25-28] The estimated activation energy and capture cross section of the T1 and T2 traps may suggest the impact of a hydrogen related center, the divacancy-hydrogen V2H trap (∆E of 0.45 eV and a sn in the 10-17 cm2 range[25,26]) for T1 and VOH trap (∆E of 0.32 eV and a sn in the 10-15 cm2 range[25,26]) for T2. The third identified trap (T3) presents an activation energy and capture cross section close to those reported in the literature for the phosphorus-vacancy complex trap V-P (∆E of 0.44 eV and a sn in the 10-14 -10-15 cm2 range[25,27]). (b) (b) (a) Fig. 4 (a) Arrhenius plot and (b) estimated GR plateau (S0) versus the relaxation time constant (τ0) corresponding to the most pronounced GR contribution of spectra illustrated in Fig. 2. A least-squares linear fit with the experimental data permits to estimate the energy difference between the conduction band energy and the trap energy (ΔE = EC – ET) (from the slope) and the capture cross section σn (from the y-intercept) (Fig. 4a); employing Eq 5, the surface trap density may be estimated from the linear dependency of the S0 with τ0 (Fig. 4b). Fig. 5 (a) Arrhenius plot and (b) estimated GR plateau (S0) versus the relaxation time constant (τ0) for the device of Fig. 2 operated at a constant applied drain current polarization of 2 µA (VDS =50 mV) in order to guarantee a constant quasi-Fermi level in a temperature range of 300 K to 330 K (a)
edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 12 Divacancies are reported to have ∆E of 0.42 eV and a sn in the 10-15 cm2 range for the single negatively charged acceptor state (0/-) V2(0/-) trap; [25,27] ∆E of 0.23 eV and a s n in the 10-15 to 10-16 cm2 range for V 2(0/+) trap, [25] and ∆E of 0.23 eV and a sn in the 10-15 to 10-16 cm2 range[25,26] for V 2(-/--) trap. Consequently, T4, T5 and T6 corresponds to V2(0/-), V2(0/+) and V2(-/--) traps, respectively. An activation energy of 0.17 eV may be linked both to traps related to the oxygen-vacancy complex (V-O) or to the interstitial–carbon–substitutional carbon complex CiCs.[25,28] The capture cross section s n is reported to be in the range of 10-14 cm2 for V-0,[28] while no value of s n for the CiCs complex is reported in the literature to our knowledge. As the CiCs complex is rather unlikely, and considering the estimated capture cross section of the trap, it is more reasonable to consider that T7 may be attributed to the oxygen-vacancy (V-O) pair. The nature of the T8 trap, characterized by a ∆E of 0.53 eV and a sn of around 10-14-10-15 cm-2 cannot be specified, due to lack of availability of bibliographical data. The main identified traps may be linked to divacancies (V2(0/-), V2(0/+) and V2(-/--)), to hydrogen (V2H and/or VOH), to phosphorus-vacancy complex (V-P), and the oxygenvacancy complex (V-O). The presence of divacancies could Fig. 6 Temperature evolution of the Sv,GR(fa,T)·fa , Sv,GR(fa,T) representing the GR noise level estimated from the experimental spectra at an imposed frequency fa of 60 Hz for the V2H trap identified in Fig. 5. fa is chosen to respect the conditions 2πfaτ0(Tmin) = fa/f0(Tmin) >>1 and 2πfaτ0(Tmax) = fa/f0(Tmax) << 1, f0(Tmin) and f0(Tmax) being the characteristic frequencies GR noise at the temperature limits (Tmin and Tmax) where this trap is active. From the maximum of the bellshaped behavior of SGR(f0, T)·fa the volume trap density may be estimated using Eq 6. The experimental B coefficient, expressed as Bexp = is consequently estimated at about 0.6, around a factor of 2 higher than the expected theoretical value evaluated for conventional planar transistors with one gate. Table 1 Different identified trap parameters Trap Activation energy, ∆E, eV Capture cross section, σ, cm2 Temperature range T, K Devices T1 0.45 3-6·10-17; 0.35 – 3.1 10-17 5·10-17; 5·10-17 0.2·10-17 1.6·10-17 250-300 240-280; 200-280 260-300 300-330 Standard UTBOX,[18,19] Rotated UTBOX [18;17] Si/SiGe superlattice I/O n-channel FinFET[15] GAA NW FET[20] T2 0.32 0.6·10-15 0.3·10-15; 0.4·10-15 1.3·10-15 210-250 210-270; 250-300 220-260 Standard UTBOX[17] Rotated UTBOX[17,18] Si/SiGe superlattice I/O n-channel FinFET[15] T3 0.44 1.3·10-14 - 3·10-14; 1·10-15; 5·10-14; 4·10-14 - 2·10-15; 2·10-15 0.76·10-14 210-300; 220-290 200-280; 300-310 240-260 Standard UTBOX[16-18] Rotated UTBOX[18,19] Si/SiGe superlattice I/O n-channel FinFET[15] T4 0.42 1.2·10-15; 4·10-15; 0.3-2.5·10-15 0.3-1·10-15; 0.4·10-15 3.8·10-15 1.4·10-15 0.67·10-15 200-250; 200-230 240-280; 285-295 220-260 300-325 300-340 Standard UTBOX[17-19] Rotated UTBOX[17,19] Si/SiGe superlattice I/O n-channel FinFET[15] GAA NS FET[21] GAA NW FET[20] T5 0.23 0.7·10-16 0.9·10-16 90-200 200-270 Standard UTBOX[16] Rotated UTBOX[17] T6 0.2 1·10-15 80-150 Standard UTBOX[16] T7 0.17 2·10-14 77-110 Standard UTBOX[19] T8 0.53 1.5·10-14 2.1·10-15 220-260 270-320 UTBOX[16] Si/SiGe superlattice I/O n-channel FinFET[15]
edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 (continued on page 16) be explained by the recombination or the evolution to a stable state of unstable defects like Frenkel pairs, which could be generated during the channel implantation. The traps related to hydrogen may be present due to hydrogen incorporated during the selective epitaxial growth (SEG) of the raised source/drains from the SiH4 precursors used in chemical vapor deposition. The traps related to phosphor may also be associated with the HDD implantation. It may be noticed there are a number of traps that are frequently found in all technologies investigated, as T1 and T4, which are observed in all UTBOX, FinFET and GAA devices. Some traps are active only in UTBOX devices, as T5 and T6. The trap nature cannot be confirmed only for T8. Other systematic studies of the low frequency noise versus temperature effectuated in 32 nm n-channel tri-gate FinFET technologies underline that the additional process steps employed to boost the devices, as uniaxial and/or biaxial global strain to increase the device mobility and selective epitaxial growth of SiGe in the source and drain regions to reduce the device access resistance may lead to an increase of the number of the unknown trap, namely traps for which the nature cannot be confirmed.[13] However, for the investigated sub 16 nm technology nodes only for one trap (T8) the trap nature cannot be confirmed and the number of the detected traps seems to decrease for more advanced technologies. This may suggest that the passage from more nanoscaled device dimensions was accompanied by a maturity of the technological processes. IDENTIFIED TRAPS IN PASSIVE DEVICES Low frequency noise measurements were performed in heavily in-situ phosphorus doped polycrystalline silicon (polysilicon) serpentine resistance before and after irradiation. The samples were irradiated in the mono-energetic proton facility (KVI-CART). A monoenergetic beam of protons at 184 MeV with a flux of 8x107 p/cm².s was used.[22] A typical example of low frequency noise spectra is illustrated in Fig. 7a. It may be observed that the pristine sample exhibits only flicker and white noise contribution, (b) Fig. 7 (a) Only flicker and white noise are necessary to obtain the best agreement between experiment and model of (2) for the pristine sample (solid gray line). Three additional GR contributions are necessary to fit the irradiated sample (solid gray line). The 1/f tendency is represented by the short-dot line. T=300 K at fixed current of 60 µA. (b) GR noise evolution with the temperature for the irradiated sample at a fixed current of 60 µA. (a) while the irradiation clearly induces additional GR noise contribution. The evolution of the low frequency noise at fixed polarization with the temperature is plotted in Fig. 7b. Low frequency noise spectroscopy was performed in a temperature range of 300 to 330 K. Defects related to divacancies V2(-/--) (∆E of 0.42 eV) and V2(0/-) (∆E of 0.23 eV) and related to phosphorus-vacancy complex (V-P). The presence of divacancies (V2(-/--) and V2(0/-)) may be explained by recombination or evolution to a stable state of the unstable defects like Frenkel pairs, which could be generated during the irradiation, while the activation of the phosphorus vacancy complex (V-P) after irradiation process may be related to the fact that the samples are highly doped with phosphorus.
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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 27 NO. 1 16 CONCLUSIONS The evolution of the characteristic relaxation time constant of the GR noise as a function of the polarization at fixed temperature and fixed drain current and applied gate to source polarization as a function of temperature allow evaluation of the presence of traps located in the depleted region of the devices. It is observed that the number of traps for which the nature cannot be confirmed for the investigated sub 16 nm technologies is low. Moving toward more scaled device dimensions, i.e., from UTBOXs to FinFETs and from FinFETs to GAA transistors the number of identified trap decreases, suggesting that the fabrication process gained maturity. The study of the GR noise was also successfully employed to identify traps created by proton irradiation of passive components, as in in-situ phosphorus doped polycrystalline silicon serpentine resistances. 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Hallen, et al.: “Lifetime in Proton Irradiated Silicon,” Journal of Applied Physics, 1996, 79(8), p. 3906-3914, doi.org/10.1063/1.361816. 27. J.A. van Vechten: “Vacancies, Dislocations, and Carbon Interstitials in Si,” Physical Review B, 35(2), p. 864-880, doi.org/10.1103/ PhysRevB.35.864. 28. S.K. Bains and P.C. Banbury: “AC Hopping Conductivity and DLTS Studies on Electron-irradiated Boron-doped Silicon,” Semiconductor Science and Technology, 1987, 2(1), p. 20-29, doi.org/10.1088/ 0268-1242/2/1/003. LOW FREQUENCY NOISE SPECTROSCOPY (continued from page 13)
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