edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 22 The selected test case for validating the CMx-ray metric was the Nvidia P100 GPU, a high-performance computing (HPC) model renowned for its advanced semiconductor technology, particularly its integration of CoWoS technology. The focus for this validation was a specific scan area near the chiplet interfaces of the P100 GPU, which included an array of intricate and critical features. This area was chosen for its rich diversity package level interconnects and wire bonds such as TSVs, microbumps, RDLs, and C4 bumps. Each of these features varies significantly in di- mensions and complexity, making them ideal for a compre- hensive test of the compatibility profile and its capabilities. The CMx-ray metric’s evaluation involved setting DFI thresholds at various multiples of the resolution, which, in this instance, was an exceptionally high 0.5 microns. This high resolution was pivotal in assessing the ability of CMx-ray to discern extremely fine features. The DFI profile (as illustrated in Table 3) indicated that the three DFI parameters linked to the visibility of finer features had negative or zero compatibility scores. This Table 3 X-ray compatibility profile generation for a test sample showing compatibility scores for individual DFI parameters Notation DFI Parameters Threshold value R=5um Test Value Cn Wm CMx−ray (-1 to 1) Pb Bump pitch 100R 870um 0.742 0.25 Sbr Bump-RDL spacing 75R 470um 0.157 0.20 Srr RDL-RDL spacing 50R 170um -0.502 0.10 +0.343 Pi RDL interconnect pitch 25R <50um -0.689 0.10 Srt RDL-TSV spacing 10R 50um 0.000 0.10 Pt TSV pitch 25R 1400um 0.981 0.25 Fig. 12 The internal structure of the package including C4 bumps and TSVs showing good x-ray compatibility. Fig. 11 X-ray image proof justifying the low compatibility scores of Srr and Pi.
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