edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 2 The semiconductor industry has consistently reinvented itself, transitioning from discrete components to integrated circuits, and from large-scale mainframes to personal computers and smartphones. Today, the industry is undergoing another transformation into the artificial intelligence (AI) era. In 2012, AlexNet won the ImageNet competition using a convolutional neural network with 62.3 million parameters.[1,2] Since then, complexity has soared and rumors suggest that OpenAI’s state-of-the-art Generative Pretraining Transformer (GPT) model contains a total of 1.7 trillion parameters.[3] The demand for computational resources has grown significantly and shows no sign of slowing. During the PC revolution, computational capacity grew ~100x per 10 years. In just eight years, Nvidia has increased AI computing by ~1000x through advances in system, software, and silicon. The increase in the scale of silicon has been tremendous. The original AlexNet model was run on two GPUs. Today’s advanced AI models utilize 1000s of GPUs, all fully networked together, functioning collectively as one massive silicon device running one parallel workload. Figure 1 illustrates the growth in GPU capabilities over time, correlating to enhancements in architecture, process technology, and packaging. Between 2014 and 2017, additional gains in computing power for each architecture were achieved by scaling process technology and enlarging GPU size. However, once the GPU size reached the reticle limit of 858 mm², further advancements were driven exclusively by architecture and process technology improvements. In 2024, advanced packaging has allowed for a twofold increase in both GPU area and transistor count by merging two reticle-sized dies into a single package. But the full impact is broader. The combination of advanced packaging with innovations in networking devices and software has made it possible for many 1000s of GPUs to communicate AUGUST 2024 | VOLUME 26 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL DEMAND FOR AI COMPUTING WILL SHAPE FA COMMUNITY James Chambers, Nvidia jichambers@nvidia.com edfas.org (continued on page 25) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Mary Anne Fleming Director, Journals, Magazines & Digital Media Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Space Systems Rosalinda M. Ring NenoVision Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2024 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Fig. 1 GPU area and transistor count versus GPU architecture year. Chambers
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