edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 16 challenging. With BEOL scaling faster than interconnect level, the distinction between them is gradually blurring, leading to ambiguity in categorizing die-level and packagelevel faults. New challenges also arise from factors like increased die size, reduced package thickness, and the introduction of novel materials in 2.5D or 3D interconnect architectures (Fig. 3), posing significant hurdles to traditional failure analysis (FA) methods. Nondestructive techniques have long been essential in IC packaging FA, offering the ability to localize defects and faults within complex structures while preserving their functionality for further testing.[10] Methods such as x-ray microscopy,[11-14] scanning acoustic microscopy (SAM),[15] time domain reflectometry (TDR),[16] and THztime domain spectroscopy (TDS), among others, enable detailed internal inspection of devices, facilitating accurate identification of failure locations and mechanisms. However, the ongoing evolution of 3D architectures and the decreasing pitch in PCB, substrate, and package interconnects like microbumps and RDLs necessitate new approaches for timely product releases and transition to high-volume manufacturing. As the electronics sector develops increasingly complex and integrated structures, the need for advanced techniques across all supply chain levels becomes paramount. For high-resolution imaging of advanced packaging interconnects, new nondestructive methods are required. Other technologies like SAM or TDS, although capable of penetrating all layers in advanced packaging, often produce inadequate signal-tonoise ratios and require additional sample preparation to identify buried failure locations. The innovative 3D x-ray systems represent a significant leap in semiconductor packaging, PCB, and wafer imaging at submicron resolution. The Sigray APEX-150 system, for instance, boasts a patented architecture, a high-flux source, a high-efficiency detector, and a software algorithm capable of achieving 0.5 µm voxel acquisition in just 3-5 minutes on any section of a package, board, or 300 mm wafer.[17] This novel 3D x-ray system architecture allows for imaging a region of interest (ROI) in large objects, such as PCBs and 300 mm wafers, from a very close distance to the x-ray source. The Sigray APEX system can resolve features as small as 3-micron diameter TSVs and 6-micron Sn(Ag) microbumps in 3D images from 300 mm wafers, with imaging times as short as 2 minutes per field of view (FOV). In the realm of increasingly miniaturized IC packaging, there’s a fundamental problem: shrinking feature sizes. This miniaturization directly impacts the capacity for physical inspection, as the dimensions of the features become smaller, demanding higher resolution for effective observation. Additionally, the assembly of more noise-inducing features in a compact space exacerbates the challenge, complicating the clarity and accuracy of inspections. A critical aspect of this challenge is the difficulty in observing features in the upper layers of the package, particularly closer to the dies. Ascending within the package structure, the dimensions of elements like bumps and other features diminish, making them harder to discern and analyze accurately. Thus, the pressing question that emerges is whether advancements in hardware and x-ray image acquisition techniques can keep pace with the relentless miniaturization of IC package features. The trend in node technology development, as depicted in Fig. 4, is rapidly approaching its physical limits, and while x-ray resolution has been striving to match this progression, the advent of stacked packaging is driving miniaturization even further. It is anticipated that the enhancement in resolution will eventually reach a plateau, a point beyond which further improvements may be constrained by physical or technological limitations. In conclusion, the ongoing trend of miniaturization implies that the physical inspection of certain fine-pitch features will become increasingly crucial over time. This necessitates a continuous evolution in inspection methodologies and technologies to effectively address the challenges posed by the ever-decreasing size of components in advanced IC packaging. DESIGN FOR INSPECTION The concept of design for inspection (DFI) is proposed, which is broadly defined as the practice of designing integrated circuit packages in a manner that facilitates easy and accurate inspection. Importantly, DFI is not confined to x-ray imaging alone; it encompasses a wide range of failure analysis and physical Fig. 3 Critical features in a 2.5D advanced IC package.
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