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A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2024 | VOLUME 26 | ISSUE 3 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org DEFECT DETECTION OF BGA SOLDER USING DEEP LEARNING WIRE BONDING IN POWER MICROELECTRONIC DEVICES 50TH ANNIVERSARY: ISTFA 2024 PREVIEW 4 28 35 ADVANCED IC PACKAGES FOR X-RAY INSPECTION 14

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2024 | VOLUME 26 | ISSUE 3 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org DEFECT DETECTION OF BGA SOLDER USING DEEP LEARNING WIRE BONDING IN POWER MICROELECTRONIC DEVICES 50TH ANNIVERSARY: ISTFA 2024 PREVIEW 4 28 35 ADVANCED IC PACKAGES FOR X-RAY INSPECTION 14

edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS AUGUST 2024 | VOLUME 26 | ISSUE 3 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS DEPARTMENTS Assessing Compatibility of Advanced IC Packages to X-ray Based Physical Inspection M. Shafkat M. Khan, Chengjie Xi, Nitin Varshney, Aslam A. Khan, Hamed Dalir, and Navid Asadizanjani This article proposes development of a novel metric designed to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. Author Guidelines Author guidelines and a sample article are available at edfas. org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 14 2 GUEST EDITORIAL James Chambers 35 SPECIAL ISTFA 2024 PREVIEW Yan Li 37 ISTFA EXHIBITORS LIST 38 2024 PHOTO CONTEST 39 2024 VIDEO CONTEST 40 EDUCATION NEWS Bhanu Sood 41 INTERNET RESOURCES Rosalinda Ring 42 DIRECTORY OF FA PROVIDERS Rosalinda Ring 44 LITERATURE REVIEW Michael R. Bruce 46 PRODUCT NEWS Ted Kolasa 48 TRAINING CALENDAR Rosalinda Ring 50 GUEST COLUMN Lun Chan 52 IN MEMORIAM 52 ADVERTISERS INDEX Reliability and Optimization of Wire Bonding in Power Microelectronic Devices Norelislam El Hami, Aicha Koulou, and Abdelkhalak El Hami A numerical investigation of the probabilistic approach in estimating the reliability of wire bonding is presented along with a reliability-based design optimization methodology (RBDO) for microelectronic devices structures. 28 For the digital edition, log in to edfas.org, click on the “News & Magazines” tab, and select “EDFA Magazine.” Nondestructive Defect Detection in 3D X-ray Microscopy Data of Ball Grid Array Solder for Void Detection in Solder Joints using Deep Learning Kishansinh Rathod, Sankeerth Desapogu, Andreas Jansche, Timo Bernthaler, Daniel Braun, Stephan Diez, and Gerhard Schneider A deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy is presented. 14 4 28 ABOUT THE COVER “Cake-all-around.” False-color 3D rendering of a FIB-SEM tomography dataset acquired from a gate-all-around test structure. The visualization was virtually cut open to gain insight into the internal structure of the sample. Photo by Heiko Stegmann, Carl Zeiss Microscopy GmbH, First Place Winner in False Color Images, 2023 EDFAS Photo Contest.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 2 The semiconductor industry has consistently reinvented itself, transitioning from discrete components to integrated circuits, and from large-scale mainframes to personal computers and smartphones. Today, the industry is undergoing another transformation into the artificial intelligence (AI) era. In 2012, AlexNet won the ImageNet competition using a convolutional neural network with 62.3 million parameters.[1,2] Since then, complexity has soared and rumors suggest that OpenAI’s state-of-the-art Generative Pretraining Transformer (GPT) model contains a total of 1.7 trillion parameters.[3] The demand for computational resources has grown significantly and shows no sign of slowing. During the PC revolution, computational capacity grew ~100x per 10 years. In just eight years, Nvidia has increased AI computing by ~1000x through advances in system, software, and silicon. The increase in the scale of silicon has been tremendous. The original AlexNet model was run on two GPUs. Today’s advanced AI models utilize 1000s of GPUs, all fully networked together, functioning collectively as one massive silicon device running one parallel workload. Figure 1 illustrates the growth in GPU capabilities over time, correlating to enhancements in architecture, process technology, and packaging. Between 2014 and 2017, additional gains in computing power for each architecture were achieved by scaling process technology and enlarging GPU size. However, once the GPU size reached the reticle limit of 858 mm², further advancements were driven exclusively by architecture and process technology improvements. In 2024, advanced packaging has allowed for a twofold increase in both GPU area and transistor count by merging two reticle-sized dies into a single package. But the full impact is broader. The combination of advanced packaging with innovations in networking devices and software has made it possible for many 1000s of GPUs to communicate AUGUST 2024 | VOLUME 26 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL DEMAND FOR AI COMPUTING WILL SHAPE FA COMMUNITY James Chambers, Nvidia jichambers@nvidia.com edfas.org (continued on page 25) PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Mary Anne Fleming Director, Journals, Magazines & Digital Media Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Michael DiBattista Varioscale Inc. Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Space Systems Rosalinda M. Ring NenoVision Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2024 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Fig. 1 GPU area and transistor count versus GPU architecture year. Chambers

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 4 EDFAAO (2024) 3:4-11 1537-0755/$19.00 ©ASM International® NONDESTRUCTIVE DEFECT DETECTION IN 3D X-RAY MICROSCOPY DATA OF BALL GRID ARRAY SOLDER FOR VOID DETECTION IN SOLDER JOINTS USING DEEP LEARNING Kishansinh Rathod1, Sankeerth Desapogu1, Andreas Jansche1, Timo Bernthaler1, Daniel Braun2, Stephan Diez2, and Gerhard Schneider1 1Materials Research Institute – Aalen University, Aalen, Germany 2BMW AG, Munich, Germany kishansinh.rathod@hs-aalen.de VOID DETECTION IN SOLDER JOINTS In the world of microelectronics assembly, soldering is a fundamental and crucial process for connecting semiconductor devices with PCBs.[1,2] The solder balls present in ball grid array (BGA) packages play a crucial role in creating this connection by forming solder joints with the corresponding pads on the PCB. The quality of a solder joint directly impacts the functionality and reliability of electronic devices.[3] One of the significant challenges faced in electronic assembly is the presence of voids within solder balls.[1,4] These voids can be formed because of many factors such as poor flux coverage, improper substrate outgassing, and reflow conditions.[5,6] The presence of these voids can have a negative impact on the performance of microelectronic devices. For example, voids can lead to increased electrical resistance, thermal impedance, and a negative impact on mechanical stability and stress concentra- tions.[4–7] Eventually, these effects can lead to breakdown or malfunctioning of the device. However, it is important to note that all voids cannot be classified as defects. For example, the current IPC A-610 standard specifies that voiding that exceeds 30% (25% as a previously applied IPC A-610 standard) of the x-ray image area is considered a defect.[8–10] Moreover, the negative impact of voids is based on their location within solder joints.[9] Therefore, it becomes very necessary to detect the voids accurately in order to quantify them correctly. X-ray inspection has emerged as a widely used tech- nique for void detection in electronic assemblies. Traditional 2D x-ray methods are commonly used due to their speed and cost efficiency.[11] A variety of traditional and machine learning-based methods and approaches have been proposed and used for the BGA solder ball’s void detection in 2D x-ray images. Peng et al.[12] proposed a novel approach using a blob filter for the automatic detection of voids in BGA x-ray images. The proposed blob filter uses the local image gradient magnitude and different-sized average box filters for multi-scale analysis. It compares the brightness differences between a blob region and its neighbors for blob enhancement. The method also uses a contrast enhancement technique and a morphological method for region growing and connecting open regions. The voids are detected based on the roundness of the region. Said et al.[13] proposed an algorithm that uses histogram and morphological-based segmentation methods for solder balls in 2D x-ray images. A voting procedure is used to segment the occluded balls. The algorithm also used an independent edge detection method to identify voids in solder balls. Ahuja et al.[14] proposed void detection based on a multidirectional scanning algorithm where the Laplacian of Gaussian is used to detect the edges. Connected component labeling is applied to separate each void region. Krammer et al.[15] investigated different traditional image processing-based methods such as Canny edge detection, global thresholding, adaptive thresholding, and blob detection for void detection. Xia et al.[16] used a 2D x-ray-based void detection algorithm that uses a dynamic enhancement algorithm to pre-process the background interference image and perform the threshold-based segmentation.[16] Schiele et al.[17] proposed an approach to segment voids in microelectronics using a convolutional neural network (CNN). Various CNN-based architectures such as U-Net and Mask-RCNN are implemented and compared.

edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 Neerula et al.[18] proposed a deep-learning approach. The U-Net architecture is used for void detection. Wankerl et al.[19] used fully convolutional networks for 2D x-ray void segmentation. The encoder of the network is inspired from the VGG network. Cheng et al.[20] proposed a novel effective fusion network for BGA bubble segmentation with blurred boundaries. A combination of the transformer and CNN network is used and to deal with limited data situations data-efficient image transformers (DeiT) are used. Though 2D x-ray methods are widely used, these methods face challenges in providing accurate information on the 3D shape, size, and location of voids within the solder joint. Moreover, details of overlapping voids are challenging to accurately obtain from 2D methods.[11,21] To address the challenges with 2D x-ray methods, technology that provides high-resolution 3D information, such as x-ray microscopy (XRM), is gaining popularity.[22,23] XRM provides precise visualization of void morphology and spatial distribution, delivering valuable 3D information.[21,22] While XRM offers significant advantages over 2D x-ray, a major challenge associated with this technique is the generation of large amounts of data. The analysis of this data can be very time-consuming and requires significant intervention from field experts.[22–25] Eom et al.[26] proposed hybrid two-stage algorithms for defect detection on occluded BGA balls. The first stage uses image processing techniques, and the second stage uses the 3D x-ray technique oblique computed tomography. Zhang et al.[27] proposed an algorithm for common defect detection which also includes voids in 3D x-ray images of BGA solder joints. The method involves analyzing crosssection images of the solder joints, segmenting the BGA ball and background, extracting features of solder joint defects, and applying decision rules for inspection. Despite the methods and algorithms proposed, accurate automated segmentation of the BGA solder voids in 3D XRM data is still challenging. Therefore, the objective of this research is to develop a deep-learning approach for an automated segmentation of the BGA solder voids. EXPERIMENTAL PROCEDURES EVALUATION AND DESCRIPTION OF THE DATASET The dataset used in this study comprises 3D x-ray microscopy scans of two different BGA samples. Thus, the dataset consists of a total of two 3D scans with each scan containing more than 1000 2D slices with a resolution of voxel size of 3.7 mm3, ensuring detailed coverage of the sample geometry. Out of these two scans, one scan is used for the training set and one is used as a test set. Data acquisition was performed using a Zeiss Xradia Versa x-ray microscope.[28] The majority of XRM scanning parameters, such as projections, binning, and voxel size, were kept identical in both scans. However, parameters like voltage, current, and exposure time were adjusted by the image acquisition expert, based on the specific characteristics of each BGA sample to optimize image quality. Third-party software Dragonfly[29] is used for 3D data visualization, data pre-processing, and data labeling for segmentation model training. As part of the pre-processing, both scans were cropped to remove unnecessary information from the 3D scan in order to optimize the computational resources. The final remaining dataset contains the void region. The labeling of this cropped dataset was done manually with three labels: voids, solder balls, and background. Further, cleaning and adjustment of labels were done using connected component analysis. The labels were validated by subject experts to ensure accuracy and reliability. However, it is important to note that even after expert validation, the labels may contain some degree of human labeling error. The data set from the training data is visualized in Figs. 1-3. Figure 1 is a visualization of XRM scans of multiple solder balls. Figures 2 and 3 visualize the sample dataset that was used for training. Fig. 1 3D XRM scans of multiple solder balls; the visualization is extracted from Dragonfly. (a) Visualization of 3D XRM volume where voids and solder balls are visible and marked. (b) 3D visualization of solder balls by removing air from actual 3D volume for better visualization of solder balls. (b) (a)

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 6 APPLIED AND TESTED DEEP LEARNING MODELS AND EVALUATION METRICS These experiments tested four different U-Net[30] architectures: U-Net 2D, U-Net++,[31] U-Net 3D,[32] and a modified U-Net 2D. In the modified U-Net 2D, a drop-out layer was added after each convolutional block of U-Net’s original model to avoid overfitting on limited training data. In addition to selecting the architecture, the impact of different loss functions on model training is also investigated. Categorical cross-entropy (CCE), Dice loss, and Jaccard loss are tested with all model architectures.[33] This comparative approach allows identifying the most suitable model and combination of loss functions for accurately detecting voids within solder balls. A third-party software, Dragonfly,[29] is used for deep learning model training. This software offers functionalities to handle and visualize 3D data. The AI modules within the software provide a no-code-based solution for different deep learning model training. To ensure consistency and fair performance comparison across the different U-Net models, all models were trained from scratch within an identical training environment. The Adadelta[34] optimizer was used to optimize the model parameters during the training process. Early stopping and reduced learning rate on plateau techniques were implemented during training to prevent overfitting and enhance generalization performance. (a) (b) Fig. 2 Region of interest visualization of 3D XRM data of solder balls and its label. (a) 3D visualization of the region of interest extracted from raw XRM data, having nine solder balls. (b) Corresponding label in 3D (3D data sliced to the half for better visualization of voids inside solder balls), where green indicates the solder balls and red indicates the voids. (a) (b) Fig. 3 Region of interest visualization of 2D XRM slice extracted from 3D XRM data of solder balls and its corresponding 2D label. (a) 2D slice (region of interest), and (b) corresponding label in 2D, where green color indicates solder ball (marked in a circle), red color is void in solder balls (marked in a square), and purple color is background.

edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 To evaluate the performance of the trained models, F1 score and intersection over union (IoU) metrics are used.[33] The IoU score is mathematically represented as: (Eq 1) where J is Jaccard distance, A is ground truth, and B is prediction. A higher IoU score signifies a greater degree of overlap between model predictions and manually annotated image regions like voids, indicating better model performance. The F1 score is calculated as: (Eq 2) where TP is number of true positives, FP is number of false positives, and FN is number of false negatives. RESULTS AND DISCUSSION The quantitative and comparative analysis of the tested U-Net models for void detection in BGA solder joints is presented in Table 1. The score present here is achieved from the test set, which is not part of the training process. Among all four models, the U-Net 2D with Dice loss and U-Net++ with CCE loss outperform the other models. Both models achieved the same IoU and F1 score, 87.7% and 92.5%, respectively. U-Net with CCE loss was not the best-performing model among other loss functions, it provided a score very near to the best-performing model, U-Net++ with CCE loss and U-Net 2D with Dice loss. U-Net with CCE provided 87.5% IoU score and 92.2% F1 score. U-Net 3D with Jaccard loss exhibited the lowest performance among all models, achieving an IoU score of 73% and an F1 score of 63%. This suggests that the architecture selection may have a significant impact on model performance. From Table 1, it is observed that overall 2D models performed better than 3D models in terms of IoU and F1 score, particularly U-Net 2D with Dice loss and U-Net++ with CCE loss outperformed other models. Figure 4 presents the results obtained from the U-Net 2D model, showing the segmentation of voids within the XRM scan of solder balls. Figure 4a is the XRM scan of solder balls from the test set, with the background Table 1 Quantitative and comparative analysis of different U-Net architectures with different loss functions tested in this study. The results shown in the table are obtained on the test set. Deep learning model Lossfunction Mean IoU,% Mean F1,% U-Net 3D CCE 81.90 88.60 Dice loss 66.50 76.80 Jaccard loss 63.10 73.10 U-Net 2D CCE 87.50 92.20 Dice loss 87.70 92.50 Jaccard loss 86.60 91.80 U-Net++ 2D CCE 87.70 92.50 Dice loss 84.90 91.10 Jaccard loss 86.60 91.80 U-Net 2D (Dropout) CCE 85.80 90.60 Dice loss 86.80 91.80 Jaccard loss 87.30 92.20 Fig. 4 Qualitative analysis of model prediction for void detection. (a) 3D XRM scan visualization from test set having nine solder balls containing voids in it, and (b) corresponding segmentation from the U-Net 2D model, visualized in 3D and overlaid on the original image, where red color is voids in the solder ball and background is removed for better visualization. (a) (b)

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 8 removed to enhance visualization. It’s important to note that the background has been removed in Fig. 4a for better visualization; the input data to the model consists of the original background. Figure 4b shows the overlay of the segmented solder voids of corresponding data by the U-Net 2D model with Dice loss, visualized in 3D. The model is applied individually to each slice in 2D, and the resulting predicted slices are stacked up and combined to generate a 3D visualization of the data using the Dragonfly software. This overlay provides a comprehensive representation of the voids detected within the solder balls, offering insights into their spatial distribution and morphology. Furthermore, in Fig. 4b, the overlay of only the predicted voids on the original input image is shown. To enhance the visualization of voids, the model prediction of background and solder balls is not included in the overlaid image. Also, the color intensity is adjusted for a clearer representation of the voids within the solder balls. This visualization aids in the qualitative assessment of the model’s performance, facilitating the identification of voids and their characteristics within the XRM scans of solder balls. Overall, Fig. 4 provides a detailed insight into the segmentation results achieved by the U-Net 2D model, highlighting its efficacy in void detection within electronic assemblies. One critical factor impacting the performance can be the volume of training data. Because each 3D scan is converted into over 1000 individual 2D slices, which are considered 2D images, the resulting 2D training dataset offers a significantly greater number of training images compared to the original 3D dataset. This amount of the training dataset provides enough resources for the models to learn the characteristics of voids. On the other hand, the dataset for the 3D model only consists of one 3D scan, which may restrict the learning capacity of the models. Additionally, the complexity of 3D data may also create challenges in learning common features of voids. These factors could potentially impact the model performance and explain the lower score of the 3D model. The graph in Fig. 5 shows a comparison of the number of voids and the distribution of voids by volume, by the deep learning model and calculated by a human operator. Fig. 5 Comparison of the volume distribution of voids (3D) and number of detected voids, by deep learning model (U-Net 2D with Dice loss) and human operator. The X-axis shows the range of volume in mm3 in the multiplication of 10e-4 and the Y-axis shows the number of detected voids in that particular volume range. Range of volume of voids in multiplication of 10e-4 (mm3)

edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 The U-Net 2D model with Dice loss is used for detection as it outperformed the other models tested. As a 2D model, it is applied individually to each slice of the test set; then these predicted slices are combined to create a 3D representation using Dragonfly software. The data showcased in the graph represent the 3D morphology obtained from the model’s predictions. The data by a human operator is obtained by manually marking the void area. The volume calculation is done by applying connected component analysis to the 3D prediction of the model. This comparison of human operator identification with deep learning model prediction allows evaluating how the deep learning segmentation model performed compared to human operators in predicting both the total number and volume of voids. The U-Net 2D model detected 71 voids, while the human operator identified 77 voids in the same sample. However as mentioned earlier, it’s important to acknowledge that human labeling may contain some degree of errors. Closer examination found that the voids not detected by the U-Net 2D model but present in the manual label data are primarily small voids falling within the range of 0.005e-8 – 2.0e-4 mm3 (in the manually labeled data). To assess the overall performance of the model, the overall volume of detected voids by the model and by the human operator were compared. The U-Net 2D model predicted a total volume of 2.05e-3 mm³, while the total volume of all voids identified by the human operator is 2.01e-3 mm³. This means the U-Net 2D model produces approximately +2% of the error rate compared to the human operator for the particular sample. To further validate the accuracy of void detection on an individual basis, five random voids were selected from the sample and their volumes were calculated. In comparison to the volumes of voids detected by the human operator, a mean error rate of approximately +3% was found for these voids. This side-by-side comparison offers valuable insights into the accuracy of void detection by the deep learning model, providing context for understanding its performance relative to human operators. CONCLUSION In this article, a deep learning-based nondestructive approach for void segmentation in BGA solder balls using 3D x-ray microscopy was presented. Various deep learning segmentation architectures with different loss functions were evaluated, including U-Net 3D. The results showed that U-Net 2D and U-Net++ outperformed the other models when combined with Dice loss and categorical cross entropy (CCE) loss respectively, achieving an intersection over union (IoU) score of 88% and an F1 score of 92%. Additionally, the comparison of the overall volume of detected voids by the deep learning model (U-Net 2D model with Dice loss) provided an error rate of +2% compared to the human operator. However, it is important to note that despite an IoU score of 88%, the models may encounter challenges in maintaining consistency across each slice of 3D scans, particularly in the presence of cracks within the solder balls. These cracks can also have a negative impact on the performance of electronic devices. Therefore, it becomes important to segment these cracks as well. Future work will address the current limitation arising by the presence of the cracks and focus on developing a model that can segment cracks independently, in addition to void segmentation in the XRM data of solder balls. Furthermore, the limitations of current 2D-based methodologies will be overcome by improving the current model for automated 3D void detection for precisely locating voids within solder balls and also providing a more accurate 3D analysis of these voids. This could eventually replace the current 2D bases IPC standard as 3D analysis provides a more comprehensive understanding of the structure and quality of solder balls. Overall, this method will contribute to the improvement of electronic device manufacturing processes. ACKNOWLEDGMENTS This work was funded by the Federal Ministry of Education and Research, Germany, in the scope of the NextGenNDT research project (grant no. 13FH566KX9). REFERENCES 1. K. Rathod, et al.: “Semantic Segmentation for Non-destructive Defect Detection in 3D X-ray Microscopy Data of Solder Joints,” 2023, unpublished. 2. PCB Assembly: Ball Grid Array Explained, Garner Osborne, 2024, www.garnerosborne.co.uk/insights/pcb-assembly-ball-grid- array-explained. 3. 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Manufacturing Processes, 2020, Vol. 57, p. 762-767, doi.org/10.1016/j.jmapro. 2020.07.021. 20. Z. Cheng, et al.: “An Effective Fusion Network for BGA Bubbles Segmentation in X-Ray Image,” 2022 5th International Conference on Pattern Recognition and Artificial Intelligence (PRAI), p. 1012–1016, doi.org/10.1109/PRAI55851.2022.9904126. 21. C. Neubauer: “Intelligent X-ray Inspection for Quality Control of Solder Joints,” IEEE Trans. Comp., Packag., Manufact. Technol. C, 1997, Vol. 20, p. 111-120, doi.org/10.1109/3476.622881. 22. C. Schmidt: “X-ray Imaging Tools for Electronic Device Failure Analysis,” Microelectronics Failure Analysis, 2019, p. 60, doi.org/ 10.31399/asm.tb.mfadr7.t91110062. 23. R.S. Pahwa, et al.: “Machine-Learning Based Methodologies for 3D X-Ray Measurement, Characterization and Optimization for Buried Structures in Advanced IC Packages,” 2020 International Wafer Level Packaging Conference (IWLPC), 2020, doi.org/10.23919/ iwlpc52010.2020.9375903. 24. H. Villarraga-Gómez, et al.: “Workflows for Assessing Electronic Devices with 3D X-ray Microscopy and Nanoscale Tomography,” e-Journal of Nondestructive Testing, 2023, 28(3), doi.org/10.58286/ 27761. 25. S. Yutai, et al.: “Volumetric Nondestructive Metrology for 3D Semiconductor Packaging: A Review,” Measurement, 2024, Vol. 225, p. 114065, doi.org/10.1016/j.measurement.2023.114065. 26. K.-Y. Eom and B. Min: “Automated X-ray Defect Inspection on Occluded BGA Balls using Hybrid Algorithm,” Computers, Materials & Continua, 2023, Vol. 75, p. 6337-6350, doi.org/10.32604/cmc.2023.035336. 27. R.Q. Zhang, X.M. Zhang, and Z. Chen: “3D X-Ray Based BGA Solder Joints Inspection Algorithm,” AMM, 2010, Vol. 29-32, p. 502-507, doi. org/10.4028/www.scientific.net/AMM.29-32.502. 28. Zeiss Xradia Versa X-ray Microscopes (2024), zeiss.com/microscopy/ en/products/x-ray-microscopy/xradia-versa.html. 29. Dragonfly 2022.2 (Computer software), Comet Technologies Canada Inc., www.theobjects.com/dragonfly. 30. O. Ronneberger, P. Fischer, and T. Brox: “U-Net: Convolutional Net- works for Biomedical Image Segmentation,” 2015, doi.org/10.1007/ 978-3-319-24574-4_28. 31. Z. Zhou, et al.: “UNet++: Redesigning Skip Connections to Exploit Multiscale Features in Image Segmentation,” IEEE Transactions on Medical Imaging, 2019, Vol. 39, p. 1856-1867. 32. Ö. Çiçek, et al.: “3D U-Net: Learning Dense Volumetric Segmen- tation from Sparse Annotation,” 2016, Medical Image Computing and Computer-Assisted Intervention–MICCAI 2016, doi.org/10.1007/ 978-3-319-46723-8_49. 33. Segmentation Models Python API — Segmentation Models 0.1.2 documentation, 2022, segmentation-models.readthedocs.io/en/ latest/api.html#losses. 34. M.D. Zeiler: “ADADELTA: An Adaptive Learning Rate Method,” 2012, doi.org/10.48550/arXiv.1212.5701. ABOUT THE AUTHORS Kishansinh Rathod has been a scientific employee at the Materials Research Institute, Aalen University of Applied Sciences since 2022. He’s currently pursuing a Ph.D. in applied machine learning for materials science (material informatics) alongside his work. Rathod received his bachelor of science degree from Sardar Patel University Anand India in 2014. He holds a master's degree from The University of Pune, India, and one from SRH Hochschule Heidelberg. Sankeerth Desapogu completed his master’s degree in engineering sciences at TH Rosenheim and since 2021 has been a student and research assistant at Materials Research Institute Aalen. There he works on semantic segmentation with deep neural networks for 2D and 3D data as well as image feature extraction for regression models. His research interests include deep neural networks and computer vision. Andreas Jansche is currently pursuing his Ph.D. in applied machine learning for materials microscopy. He received his bachelor’s degree in computer science and his research master’s degree in advanced materials and manufacturing from Aalen University, Germany. He has been working as a research assistant at the Materials Research Institute Aalen since 2015 and as a software engineer for automated microscopy and machine learning solutions since 2012.

edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 Timo Bernthaler studied materials and surface engineering at Aalen University and received his Ph.D. from the School of Materials Science and Engineering at the University of New South Wales. He has worked for over 20 years in the development and characterization of structural and functional materials. In 2019, he became managing director of Matworks GmbH Materials Engineering Solutions—a company within the Steinbeis Enterprise for industrial technology transfer. Daniel Braun works for BMW AG as a failure analysis specialist. He is the technical group leader for semiconductor failure analysis in the Materials and Process Analysis division. Braun pursued his Ph.D. at the Karlsruhe Institute of Technology in the field of tribology. He received a master’s degree in material sciences from Friedrich-Alexander-University in Erlangen-Nürnberg. Stephan Diez works as a failure analysis specialist for BMW AG. He has been technical group leader for failure analysis in the field of general automotive electrics/electronics at the Materials and Process Analysis division for several years. Gerhard Schneider is director of the Materials Research Institute, Aalen University, and a co-opted professor in the Faculty of Mechanical Engineering at the Karlsruhe Institute of Technology (KIT). He conducts research in the fields of materials analysis, functional materials, additive manufacturing, and machine learning. ESREF 2024 The 35th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2024) will take place September 23-26 at the Paganini congress in Parma, Italy. This international symposium has a focus on reliability in all aspects of electronics including new applications in extremely harsh environments such as space, transport, energy conversion, and smart functions. It provides the leading European forum for developing all aspects of reliability management and innovative analysis techniques for present and emerging semiconductor applications. For more information, visit esref2024.org. ITC 2024 The International Test Conference (ITC) will be held November 3-8 in San Diego, Calif. ITC is the world’s premier conference dedicated to the electronic test of devices, boards, and systems covering the complete cycle from design verification, test, diagnosis, failure analysis, and back to process and design improvement. At ITC, test and design professionals will confront the challenges the industry faces and learn how these issues are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. ITC, the cornerstone of TestWeek events, offers a wide variety of technical activities targeted at test and design theoreticians and practitioners. The conference includes paper sessions, keynotes, tutorials, case studies, commercial exhibits and presentations, and a host of ancillary professional meetings. ITC is sponsored by the IEEE. For more information, visit itctestweek.org. NOTEWORTHY NEWS

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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 14 ASSESSING COMPATIBILITY OF ADVANCED IC PACKAGES TO X-RAY BASED PHYSICAL INSPECTION M. Shafkat M. Khan, Chengjie Xi, Nitin Varshney, Aslam A. Khan, Hamed Dalir, and Navid Asadizanjani University of Florida, Gainesville, Florida m.khan3@ufl.edu EDFAAO (2024) 3:14-24 1537-0755/$19.00 ©ASM International® INTRODUCTION X-ray imaging has become a crucial method for postsilicon validation, offering a closer look into the internal structures and ensuring the integrity of integrated circuits (IC) and advanced packaging systems.[1,2] This technique involves capturing x-ray images from various angles to create three-dimensional models of IC devices or packages. X-ray laminography and tomography are particularly important in this process. The nondestructive nature of x-ray imaging and its ability to reveal intricate details within complex assemblies are its primary benefits. High-resolution x-ray systems enable the visualization of the complex internal structures found in advanced IC packages,[3] such as diverse system in packages (SIP) that contain multiple dies in a single package.[4] X-ray imaging facilitates fault isolation, measures the dimensions of inner circuit layers, inspects the alignment of stacked components, and evaluates the overall assembly’s integrity.[5,6] The efficiency of x-ray inspection in revealing features within ICs is largely dependent on the size of these features and the overall complexity of the design. Advanced IC packaging, characterized by its densely packed compo- nents and noise-generating elements, poses significant challenges in both the image acquisition and reconstruction phases when using x-ray tomography or laminography. The trend toward miniaturization and the high-density integration in these packaging technologies leads to reduced feature sizes and a tighter arrangement of components. Such conditions often result in overlapping or unclear details, complicating the analysis of x-ray inspection data. Moreover, factors that contribute to noise, like scattered x-ray radiation or artifacts from material interfaces, can further hinder the image acquisition process.[7] These elements can add undesired signals or distortions, impeding the precise detection and localization of defects or faults in the IC package. A notable example of this can be seen in Fig. 1, where the difference in the visibility of redistribution layers (RDL) with discernible feature sizes and those too small to resolve is evident. The development of a new metric, specifically designed for assessing x-ray inspection compatibility in semiconductor packaging design and manufacturing, marks a significant advancement in the field.[8] This metric, referred to as CMx-ray, is fashioned to be instrumental in providing designers with a concrete measure of how visible Fig. 1 Observability of fine-pitched features is influenced by the specifications of their size, dimension, and material composition. (a) (b) (c)

edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements. This enables designers to base their decisions on solid data, improving the chances of successful inspection results. For instance, the metric can help identify areas prone to noise scattering or places with spacings too small to resolve, allowing for adjustments before starting the manufacturing process. Such early interventions can optimize manufacturability, decrease the likelihood of expensive redesigns, and accelerate the product’s time-tomarket. Incorporating this metric at the pre-silicon stage represents a proactive and structured method to tackle the challenges associated with x-ray inspection, ultimately improving reliability and production yield. BACKGROUND AND MOTIVATION The evolution of IC packaging (as shown in Fig. 2) has been marked by significant transitions, reflecting the advancements in technology and the growing demands for performance and miniaturization. Initially, the industry relied on simpler formats like the single inline package and dual inline package, which set the foundation for IC packaging. However, as the need for higher pin counts and enhanced performance grew, more advanced solutions were developed, such as the pin grid array (PGA) and quad flat package (QFP). These innovations allowed for greater complexity and functionality in IC design. A pivotal shift occurred with the adoption of surface mount technology (SMT), epitomized by packages like the ball grid array (BGA) and flip-chip ball grid array (FCBGA). This transition from pins to bumps represented a significant step towards miniaturization, enabling the production of smaller, more functional ICs. This change was instrumental in accommodating the increasing demands of compact and efficient electronic devices. The latest developments in the field have been even more revolutionary, focusing on 2.5D and 3D packaging technologies. These approaches involve stacking multiple IC dies or placing them side by side. Such configurations offer substantial performance gains and a reduction in form factor, crucial for the current era of high-performance computing. These innovations are at the heart of cutting-edge technologies, driving progress in sectors like data centers and high-performance computing, with applications in advanced products like GPUs, APUs, FPGAs, and more. Each of these steps reflects the ongoing journey of IC packaging, showcasing an industry continuously pushing the boundaries of what’s possible in electronic component design and functionality. When we discuss the incredible advancements in microelectronics today, it’s essential to focus on the interconnect level, particularly at die-to-die and dieto-substrate interfaces. This focus is crucial for implementing various packaging technologies while ensuring reliability and longevity. The ongoing adaptation of the redistribution layer (RDL), coupled with the development of new interconnect architectures like through-silicon vias (TSVs) and microbumps, is driven by the trend of shrinking interconnect dimensions, lower feature pitch, and thinner material layers.[9] Concurrently, back-endof-line (BEOL) processes have become more intricate, bridging the gap between rapidly scaling transistors and the slower pace of interconnect miniaturization. Modern BEOL stacks often comprise over ten metal layers, featuring complex chip-packaging interaction (CPI) structures, while TSV and bump features shrink from hundreds to tens and even single-digit micrometers in size. As a result, analyzing these intricate products and pinpointing the fundamental causes of failure, such as issues in packaging design and production techniques, has grown increasingly Fig. 2 Evolution vector of packaging in the semiconductor industry.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 16 challenging. With BEOL scaling faster than interconnect level, the distinction between them is gradually blurring, leading to ambiguity in categorizing die-level and packagelevel faults. New challenges also arise from factors like increased die size, reduced package thickness, and the introduction of novel materials in 2.5D or 3D interconnect architectures (Fig. 3), posing significant hurdles to traditional failure analysis (FA) methods. Nondestructive techniques have long been essential in IC packaging FA, offering the ability to localize defects and faults within complex structures while preserving their functionality for further testing.[10] Methods such as x-ray microscopy,[11-14] scanning acoustic microscopy (SAM),[15] time domain reflectometry (TDR),[16] and THztime domain spectroscopy (TDS), among others, enable detailed internal inspection of devices, facilitating accurate identification of failure locations and mechanisms. However, the ongoing evolution of 3D architectures and the decreasing pitch in PCB, substrate, and package interconnects like microbumps and RDLs necessitate new approaches for timely product releases and transition to high-volume manufacturing. As the electronics sector develops increasingly complex and integrated structures, the need for advanced techniques across all supply chain levels becomes paramount. For high-resolution imaging of advanced packaging interconnects, new nondestructive methods are required. Other technologies like SAM or TDS, although capable of penetrating all layers in advanced packaging, often produce inadequate signal-tonoise ratios and require additional sample preparation to identify buried failure locations. The innovative 3D x-ray systems represent a significant leap in semiconductor packaging, PCB, and wafer imaging at submicron resolution. The Sigray APEX-150 system, for instance, boasts a patented architecture, a high-flux source, a high-efficiency detector, and a software algorithm capable of achieving 0.5 µm voxel acquisition in just 3-5 minutes on any section of a package, board, or 300 mm wafer.[17] This novel 3D x-ray system architecture allows for imaging a region of interest (ROI) in large objects, such as PCBs and 300 mm wafers, from a very close distance to the x-ray source. The Sigray APEX system can resolve features as small as 3-micron diameter TSVs and 6-micron Sn(Ag) microbumps in 3D images from 300 mm wafers, with imaging times as short as 2 minutes per field of view (FOV). In the realm of increasingly miniaturized IC packaging, there’s a fundamental problem: shrinking feature sizes. This miniaturization directly impacts the capacity for physical inspection, as the dimensions of the features become smaller, demanding higher resolution for effective observation. Additionally, the assembly of more noise-inducing features in a compact space exacerbates the challenge, complicating the clarity and accuracy of inspections. A critical aspect of this challenge is the difficulty in observing features in the upper layers of the package, particularly closer to the dies. Ascending within the package structure, the dimensions of elements like bumps and other features diminish, making them harder to discern and analyze accurately. Thus, the pressing question that emerges is whether advancements in hardware and x-ray image acquisition techniques can keep pace with the relentless miniaturization of IC package features. The trend in node technology development, as depicted in Fig. 4, is rapidly approaching its physical limits, and while x-ray resolution has been striving to match this progression, the advent of stacked packaging is driving miniaturization even further. It is anticipated that the enhancement in resolution will eventually reach a plateau, a point beyond which further improvements may be constrained by physical or technological limitations. In conclusion, the ongoing trend of miniaturization implies that the physical inspection of certain fine-pitch features will become increasingly crucial over time. This necessitates a continuous evolution in inspection methodologies and technologies to effectively address the challenges posed by the ever-decreasing size of components in advanced IC packaging. DESIGN FOR INSPECTION The concept of design for inspection (DFI) is proposed, which is broadly defined as the practice of designing integrated circuit packages in a manner that facilitates easy and accurate inspection. Importantly, DFI is not confined to x-ray imaging alone; it encompasses a wide range of failure analysis and physical Fig. 3 Critical features in a 2.5D advanced IC package.

edfas.org 17 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 3 inspection modalities, thereby offering a comprehensive approach to IC package validation. The advantages of implementing DFI are readily apparent. Primarily, it significantly reduces the likelihood of producing components that are challenging to validate or analyze for failures. This proactive approach has two key positive outcomes. First, it enhances reliability testing, enabling more effective identification and mitigation of potential failure points in the IC packages. Second, it leads to improved and expedited failure analysis capabilities, which is critical in the fast-paced semiconductor industry. The development of the DFI framework (Fig. 5) is structured around three major directions: Metrology and Database Development: This aspect aligns with some of the grand challenges outlined by the National Institute of Standards and Technology (NIST). It involves developing precise measurement methods to ensure that material and structural specifications and standards are met in advanced package manufacturing. Additionally, creating a comprehensive defects database for different feature units in a package is essential for the quick and reliable identification of defects. Automated FA Tools with AI Integration: The second direction focuses on building automated failure analysis tools that incorporate AI-based models. These tools, powered by robust database infrastructure, facilitate faster and more accurate classification of feature defects. The Fig. 5 The proposed design-for-inspection framework encompassing the three major directions. Fig. 4 The trend in x-ray resolution advancement and advanced node technology progress.

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