edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 2 32 INTRODUCTION Laser voltage probe (LVP) has evolved into one of the most useful techniques applied in failure analysis. Hardware and software refinements over the last 20 years have industrialized the practice and made it the de facto standard electrical fault analysis (EFA) probe method.[1] After achieving so much success developing laserbased tools for failure analysis over the past 20 years, storm clouds are brewing. At the 2023 ISTFA conference in Phoenix there was a sense of apprehension from many in the EFA community. Concerns were driven by recently published roadmaps indicating that some of the most cutting-edge factories are preparing for a transition to buried power rail (BPR) and equivalent wafer technologies. Such a fundamental change would block optical access to the key layers needed to generate LVP signals required for debug. While BPR technologies would be incompatible with laser-based failure analysis, laser techniques will continue to play the leading role into the foreseeable future for what will likely be the vast majority of failure analysis teams. Especially for those that support diverse portfolios built using a wide variety of different technology nodes down to ~5 nm FinFET. From LVP waveform data one can observe logical switching behavior from internal circuits of interest to root cause sources of corruption, as well as measure propagation timing delay between target nodes along critical internal speed paths as shown in Fig. 1. Having the ability to probe both logical state machine behavior, as well as measure timing, provides key information to failure analysis (FA) teams when working on first silicon bring up, yield issues, or when isolating causes of one of a kind customer field returns. Differential LVP (dLVP) introduces another approach, or twist, to the popular technique.[2] In simple terms, this process simultaneously acquires waveform data from a single target while the device under test fluctuates between passing and failing test outcomes. This sounds like a contradiction, but it is accomplished by collecting waveform data while looping on a test biased at a metastable voltage, frequency, and temperature combination. The optimum setup is where the device pass rate is 50%, so that pass and fail data are acquired at an equal rate. The main reasons for developing the technique will be explained and discussed in detail, but for now, an example of a dLVP waveform recorded from a transistor in a dense 5 nm logic cell is shown in Fig. 2. To some readers, the immediate reaction is, “so this technique only works on soft fails?” And the short answer is yes, in its raw original form. However, the idea behind dLVP has inspired new hardware development. This enables new and innovative approaches on ways to effectively collect, process, and manipulate masses of high resolution LVP waveform data across much larger time spans than previously possible. Some of the ideas will be discussed toward the end of this article. The motivation of this work is to create breakthrough methods for FA and to help extend the effective life span of existing LVP toolsets; in short, to help win the war that must be fought when trying to probe the smallest nodes in 28 nm to 5 nm IC technologies. DIFFERENTIAL LASER VOLTAGE PROBE DEVELOPMENT One of the most common methods for logic-based failure analysis is to compare waveforms from good and bad die. To do this on hard failure modes necessitates DIFFERENTIAL LASER VOLTAGE PROBE: A BRIEF OVERVIEW AND THOUGHTS ON WHAT COULD COME NEXT Kristofor Dickson NXP Semiconductor kristofor.dickson@nxp.com EDFAAO (2024) 2:32-38 1537-0755/$19.00 ©ASM International®
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