edfas.org 45 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 1 overlay with the package, match field of view and zooms for ease of use between the different components of an advanced package. One participant voiced the benefit of the tool for FIB circuit edit when trying to quickly understand the obstacles that need to be milled away for the edit. The 3D view was also of interest to the audience. The software can visualize each component in 3D separately. Upcoming changes that the user base could use in layout software were then discussed. One suggestion was adding FIB edit checks. Ideally, the user could add a proposed FIB circuit edit into the software and checks would let the user know the viability of the planned edit. For instance, a consideration would be whether a sensitive circuit could be damaged, or timing altered. Another suggestion involved adding ways to extract information from layouts to build schematics when not all information is available due to cross-company data sharing issues. One participant said that this may lead to quick turn-around reverse engineering layouts, potentially with AI. brings the sensor closer compared to a SQUID which has additional standoff limited by the vacuum with cryogenics setup. Temporal resolution of logic signals is another concern due to the setups camera frame rate. A few attendees voiced their reason for not using similar magnetic field imaging techniques. Some reasons are expense, X-Y-Z resolution, and the need for short standoff heights. One participant suggested electro optical terahertz pulse reflectometry (EOTPR) as a good benchmark for comparing techniques. Some of these points lead back into the roadmap and are great discussions to continue in other forums like ASM Connect. Arshdeep Singh from Synopsys kicked off the final topic by presenting on SysNav. The software addresses the increasing complexity of advance packages by bringing the chip(s) and the associated package into one, interconnected layout setup. The resulting discussion focused heavily on capabilities and potential improvements. In response to one question, Singh described how chips can ISTFA 2023 NANOPROBING AND SPM USER GROUP Chair/Co-Chairs: Greg Johnson and Nicholas Antoniou greg.johnson@zeiss.com, nicholas@primenanoinc.com The ISTFA 2023 Nanoprobing and SPM User Group attempted this year to reflect on various trends in the industry, as inspired by categories of advanced failure analysis that were thought to be included in upcoming drafts of the roadmaps. The goal was to explore whether some of these perceived-needs in the industry reflected the need for radically new toolsets, or whether there were simply a greater need for better sharing of best practices amongst engineers in the industry. Five categories of fault isolation were chosen and the resulting combined presentation contained results from Andrew Jonathan Smith of Kleindiek, John Sanders of Thermo Fisher Scientific, Greg Johnson of Zeiss, William Hubbard of NanoElectronic Imaging, Pamel Komarov of NenoVision, Nicholas Antoniou of PrimeNano, and Phil Kaszuba, Independent Consultant. As technology nodes shrink, it will become ever more critical to provide minimal physical damage from probing, and applied energy from SEM beam scanning. This was the first round of discussion. Results were shared from traditional nanoprobing from both Kleindiek and Thermo Fisher, showing high resolution at 100 eV imaging, and nicely smooth transistor families of curves for delayered SRAMs of 5 nm technology nodes. Lorenz Lechner of Kleindiek also displayed recent successful results on a 3 nm technology node chip. Given these successes, we asked what tips the audience had for advanced technology node nanoprobing. One such answer was to use “CR10,” or 10-nm radius, probe tips for 5 nm nodes, but “CR5,” or 5-nm technology node tips, may be required for 3 nm. A question was asked as to whether CR5 tips were easily breakable, and Lechner replied that there was not a significant difference in this regard between CR5 and CR10. Another question was asked about challenges for delayering 3 and 5 nm nodes versus 14 nm. Nick Pronin of NXP answered that this was not a significant challenge as long as one is careful with the applied beam or ion energies. A slide from William Hubbard was shared, showing atomic resolution EBIC on a gold nanoparticle, as well as isolating the electric field in a HEMT device. One of the greatest technical challenges of defect localization in SRAM or logic nanoprobing is the isolation of a single fin within a multi-fin device. Results were presented from both Kleindiek and Thermo Fisher on 5 nm devices, showing either node to node resistive shorts, or the picking out of one fin from a multi-fin device. A question was asked about the greatest challenge of this kind of analysis. One answer was the difficulty of finding
RkJQdWJsaXNoZXIy MTYyMzk3NQ==