edfas.org 43 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 26 NO. 1 Nondestructive FI and FA tools and metrologies were suggested before any physical FA. An extremely careful physical FA plan was suggested. A close collaboration among FA engineers, yield or quality engineers, and test program engineers was highly recommended. In addition to technical questions, discussions around some logistic and legal issues in SIP FI-FA were also very interesting. For example, the detailed agreements of ownership and responsibility in multichip packages or SIP having more than three suppliers; JDEC standards of sharable data sheet, component functions; and good cooperation between partners. ISTFA 2023 SAMPLE PREP USER GROUP Chair/Co-Chairs: Jim Colvin, Cecile Bonifacio, and Kah Chin Cheong jim@fainstruments.com, cs_bonifacio@fischione.com, kah.cheong@samsung.com The Sample Prep User Group was held on November 15 which was the same day as the Sample Preparation Technical session. There were more than 80 attendees including vendors. The highlights of the session included discussion on device delayering, deprocessing flip-chip devices, and sample preparation of SiC power devices which was timely for ISTFA’s overall theme of power devices. Pawel Nowakowski, from Fischione Instruments, gave a short presentation on aspects of the delayering process. Nowakowski asked the audience what they need from vendors: one tool that does everything versus one that does complex process and requires multiple techniques and regarding automation and end-pointing, specifically a black box versus a user-interactive system. Wentao Qin, from Microchip Technology asked a question and engaged the audience for a discussion on how to prepare his sample. Kah Chin Cheong, from Samsung Austin Semiconductor LLC, gave a presentation called “Package Recombination in Deprocessing for Encapsulated Flip-Chip Devices.” Cheong described a cost-saving method in extracting and deprocessing an encapsulated flip-chip. The method works well for target area of interest near the die edges. Brian Tracy from Tesla Inc. asked if wet etch works better in extracting the flip-chip. Cheong responded that fuming nitric acid could be a solution. However, the method discussed is for an analysis lab with limited lab capabilities and chemical accessibility. Wentao Qin, from Microchip Technology Inc. and Steven Herschbein, an independent consultant, discussed the possibility of using tripod polishing method to replace hands-polishing. Cheong summarized his presentation by emphasizing the core value of the method is to promote creativity and find alternative solutions with limited lab resources, and in a most cost-savings way. Rosine Coq Germanicus from the University of Caen presented on sample preparation of packaged SiC devices in cross-section. The different steps of the sample preparation from the x-ray views to cross-sections were detailed for two devices. One of the questions from the audience was about the challenges of the backside preparation. Coq Germanicus explained that it is important to conserve all the top parts of the packaged device, in particular, the interface between the EMC box and the SiC chip, to fully understand the failure. In addition, this preparation is optimized to conserve also electrical access and to be able to polarize the device, for example, electrical AFM measurements or EBIC under SEM. Efrat Moyal from Zeiss asked about the cross-section SEM image of the burnout and also complimented Coq Germanicus on the impressive burnout image. Coq Germanicus showed the trace of the micro-explosion and with her colleague, co-author of the paper and an expert in fire in dense material, they were able to understand the different steps of an explosion, and in particular the off-gassing. She discussed the elements involved in the explosion: oxygen, carbon, and the destruction of SiC. The audience asked how she was able to open the backside of device and through the package Sample Prep User Group presenters and co-chairs.
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