edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 4 58 is required to fully validate the feasibility of these IEEE protocol standards for 3DIC Design for manufacturability, testability, yield, reliability, power, and cost (DFx). PRODUCT YIELD, TEST, AND DIAGNOSTICS As digital circuits become more complex and test time reduction remains a priority, it becomes imperative for DFT tool vendors to introduce automatic test pattern generation compression. However, this compression can significantly affect the accuracy and resolution of diagnostic results and the complexity of test patterns. Siemens’ introduction of streaming scan networks (SSN) has revolutionized multi-core parallel testing and provided benefits for testing and design integration. But this complex architecture poses numerous challenges to EFI as it hinders the top-level visibility of important scan signals, such as the scan clock, shift enable, and EDT update, which determine the device’s state. Additionally, the SSN hardware configuration prevents on-the-fly test vector modification and looping of test patterns needed to stimulate the device during OFI. Custom patterns and user-defined fault models provide more targeted stimulation and better diagnostics but require special setups on top of production patterns. GENERAL (LEADING EDGE TECHNOLOGIES) With the advent of nanosheets and gate-all-around technology, the metal gate completely obstructs optical access to the channels. However, laser stimulation and LVx techniques could still potentially work through interactions with the wells and junctions since the source and drain regions will likely still be accessible. The effect on photon emissions (PEM), however, is worse than laserbased techniques. This is because of the wavelength spectrum of photons involved (1200 nm and above), limiting the optical resolution to below 240 nm. Furthermore, reduction of the leakage currents and decrease in VDD voltage also reduce the photon energies, causing a red shift in the emission spectrum. To push Moore’s law beyond 3 nm, buried power rails with backside power delivery (BPD) have become part of the roadmap for fabricators like Intel, TSMC, and Samsung. This advanced technology node addresses power and performance issues that arise from routing congestion and scaling of transistors by separating the power delivery network that used to be routed together with signals and placing them directly below the transistors to mitigate IR voltage droop. However, this architecture poses a significant challenge for EFI since BPD blocks the backside of the silicon transistor layer, impeding most OFI techniques like photon emissions, laser stimulation, and laser voltage probing/imaging. Due to this dilemma, electron beam probing is making a comeback. However, this technique also comes with its own set of issues, which includes extensive sample preparation, lack of ATE docking and the need for vacuum and heat dissipation. Thus, it is essential to explore alternative fault isolation methods and improve DFT coverage and diagnostics. SYSTEM LEVEL, ANALOG/RF, AND DIGITAL FUNCTIONAL Aside from digital technology scaling challenges, there is a growing difficulty in the field of analog debug and system-level FA due to the lack of controllability and accessibility for such devices and circuits. The lack of standards for fault modeling and test coverage of analog circuits results to limited or no diagnostics at all. Current OFI techniques such as PEM and static laser stimulation mostly produce complex maps consisting of multiple spots that only provide symptoms of the defect observed, making it difficult to interpret the data. Furthermore, the use of solid immersion lenses (SIL) on a system-level bench becomes challenging due to physical limitations caused by the bench hardware having multiple components that may interfere with the SIL landing. ACKNOWLEDGMENTS The die-level fault isolation committee is dedicated to providing a roadmap that addresses the challenges mentioned above by proposing effective solutions. More details will be published on ASM Connect. We express our deepest gratitude to all the committee members who have demonstrated an unwavering commitment and invaluable expertise that are crucial to achieving our goals. Committee members focused on laser-based, photon emission, and thermal include: Venkat Krishnan Ravikumar, AMD; Kristofor Dickson, NXP; and Christian Boit, Technische Universität Berlin. Members focused on 2D/2.5D/3D package EFI include: Szu Huat Goh, Qualcomm Technologies Inc.; Lesly Endrinal, Google LLC; and Samuel Chef, Temasek Laboratories, Nanyang Technolo- gical University. Members focused on system level, analog/ RF, and digital functional include: Luc Saury, STMicroelec- tronics and Zhongling Qian, Infineon AG. Members focused on product yield test and diagnostics include: Pan Yan, Microsoft Corp. and Rommel Estores, ON Semicon- ductor Corp. Members focused on general (leading edge technologies) include: William Lo, NVidia; Tom Tong, Intel Corp.; and Ed Cole., Jr., Sandia National Laboratories.
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