edfas.org 57 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 4 GUEST COLUMN more prominent, posing more demanding optical resolution requirements to have reliable measurements. Furthermore, with the introduction of DTCO, certain design rules that aim to eliminate layout nonuniformity create an extra challenge to CAD-image alignment. To address these issues, there is a need to utilize shorter laser wavelengths. However, this comes at a cost. Visible light probing typically uses laser wavelengths between 500 to 700 nm, which require the sample to be ultra-thinned below 5 µm. This process is highly challenging and risky. More challenges that loom upon conventional EFI processes, particularly optical probing, due to continued technology scaling based on the IEEE International Roadmap of Devices and Systems (IRDS-2022) for the next five years will be discussed. 2D/2.5D/3D PACKAGING The increasing complexity of 3D IC packages is also posing a significant challenge to optical fault isolation (OFI), particularly with the many configurations (material, orientation, interconnects, stacking) that make it difficult to develop and standardize FA techniques and tools. The stacking of multiple dies obstructs the line-of-sight accessibility of intermediate dies, making it even harder to isolate faults. In addition, current x-ray, magnetic, and acoustic imaging tools require more spatial resolution (x, y, z), sensitivity, and accuracy due to the introduction of hybrid bonding and the scaling of interconnects and bump pitch below 10 μm. As more dies are integrated into one package, there is a need for standardization of testing and improved diagnostics to identify and isolate the failure to a specific logic cell within a particular die. For 3DIC fault detection and isolation using design for testability (DFT), although the solutions to identify faulty TSVs at pre-bond, die-die interconnects as well as stacked dies appears to be established from literature, more industrial silicon data The rapid advancement of today’s technology is evidenced by the emergence of novel paradigms like 5G, artificial intelligence, augmented reality, metaverse, blockchains, quantum computing, and autonomous driving, which has resulted in an increased demand for ICs to deliver higher performance at greater speeds and less power. For decades, the scaling of transistors adhered to Moore’s law until the last ten years when the exponential increase in transistor density led to escalating lithography expenses and complexity, causing substantial yield losses. To improve manufacturability and achieve optimal performance, power, area, and cost (PPAC), design technology co-optimization (DTCO) and system technology co-optimization initiatives were introduced. While efforts to improve PPAC have been successful, the shrinking of transistors, lower power consumption and drive voltage, along with the increasingly complex package technology, present additional challenges, such as electrical fault isolation (EFI). The current package technology now includes multiple component stacks with decreasing bump pitch, which is expected to reach submicron dimensions (500 nm). The Die-Level Roadmap Committee aims to identify forthcoming challenges related to EFI within the next five years and collaborate with various stakeholders, including industry, academia, and tool vendors, to devise practical solutions. To that end, the team has pinpointed five critical areas of focus: (1) laser-based, photon emission, and thermal; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) general (leading edge technologies); and (5) system level, analog/RF, and digital functional. LASER-BASED, PHOTON EMISSION, AND THERMAL With the continuous scaling of transistors from FinFET to nanosheets, laser voltage probing crosstalk becomes THE EDFAS FA TECHNOLOGY ROADMAP— DIE-LEVEL ROADMAP COUNCIL (DLRC) Lesly Endrinal, Google LLC lendrinal@google.com Szu Huat Goh, Qualcomm Technologies Inc. szuhgoh@qti.qualcomm.com
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