edfas.org 15 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 4 to have excellent adhesion to the surface. Figure 5 shows the copper and SiO2 interface from the cross section of the 60 second dwell time deposition. There appears to be conformal adhesion to the surface of the SiO2 layer. A significant amount of IC backside circuit edit work is performed with ultrathin silicon thicknesses on the order of 3-10 µm from the active circuitry.[8-10] Solutions for IC debug and diagnostics can include thermally confined depositions on a thin layer of SiO2 on top of ~3 µm of silicon above the circuit layer. The low temperature deposition reaction allows for implementation on ultra thinned backside silicon. In the case shown in Fig. 6, the 20x objective and the 532 nm laser set to a power of 100 mW and 0.5 µm/sec scan speed was used to deposit the two 20 µm x 20 µm pads. Two signals have been exposed and connected through the node access holes and brought out to the surface using FIB tungsten and connected to the adjacent LCVD pads. These pads and connections are used to physically probe the signals for interpretation and measurements during test. The surface roughness of the copper deposition is also an enabler for landing the probe pads. This work duplicates previously published work in 2006 from Janne Remes’ Ph.D. thesis[25] with the combination of FIB and laser assisted copper deposition, and demonstrates the electrical testing viability of this solution. These techniques take advantage of the low resistivity, high volumetric deposition rate, and improved timing constant for sensitive performance measurements of circuit modifications as shown in Table 1. CONCLUSIONS The introduction of complex IC packaging with 2.5D and full 3D integration requires the development of new techniques to assist with rapid diagnosis and modification of high-performance circuits. Laser-assisted copper deposition using CupraSelect with a disproportionate reaction at low temperature provides an efficient method to deposit new copper traces for IC design debug applications. The use of excess TMVS to deliver CupraSelect overcomes delivery challenges and the presence of a high background of water pressure also assists with the adhesion to the surface. Laser-based copper deposition techniques have been shown to be useful in combination with traditional FIB techniques with improved resistivity, deposition rate, and timing improvements. REFERENCES 1. D. Nuez, et al.: “Failure Localization Techniques for 7 nm and 16 nm Process Nodes in Monolithic and 2.5D SSIT Packages using OBIRCH, LVP, and Advanced Die Thinning,” Proc. Int. Symp. Test. Fail. Anal. (ISTFA), 2021, p. 73-79. 2. E. Beyne, et al.: “3D SoC Integration, Beyond 2.5D Chiplets,” 2021 IEEE International Electron Devices Meeting (IEDM), doi.org/10.1109/ IEDM19574.2021.9720614. 3. T. Li, et al.: “Chiplet Heterogeneous Integration Technology – Status and Challenges,” Electronics, 9, 2020, p. 670, doi.org/10.3390/electronics9040670. 4. J.H. Lau: “Chiplet Heterogeneous Integration,” Semiconductor Advanced Packaging, Springer, Singapore. 2021, p. 413-469, doi.org/10.1007/978-981-16-1376-0_9. 5. Y.P. Chiang, et al.: “InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021, p. 130-135, doi.org/10.1109/ECTC32696.2021.00033. 6. H. Lin, et al.: “Efficient Backside Power Delivery for HighPerformance Computing Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 30(11), Nov. 2022, p. 1748-1756, doi.org/10.1109/TVLSI.2022.3183904. 7. D. Medhat: “2.5/3D IC Reliability Verification Has Come A Long Way,” Semiconductor Engineering, 2022. Table 1 Deposition Resistivity, Volumetric Deposition Rate, and RC Timing Constant between FIB W, Pt, and LCVD CupraSelect Key metric Deposition material Ga+ FIB tungsten Ga+ FIB platinum LCVDCupraSelect Resistivity (µohm-cm) 5.6 10.6 1.67 Volumetric deposition rate (µm3/min) 5 25 1500 100 µm connection RC timing constant (tau, ps) 12.13 9.05 8.63 Fig. 6 SEM image showing two signal node access holes with pico-probe pad structures made from LCVD, connected and strapped to FIB deposited tungsten (W).
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