edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 of layers containing both metal and dielectrics. The SIMS allows the etch to stop at a precise point during delayering rather than etching blindly. The metal layers closer to the device layer can be tens of nanometers in thickness, and SIMS has sufficient accuracy to stop the etch within a target layer. As a result, ion beam delayering enables users to understand the IC for failure analysis and quality assurance. Ion beam delayering uses a broad beam of ions from a gridded ion source to sequentially etch a whole integrated circuit (IC) chip from the top metal layer to the bottom device layer. The technique delayers the whole chip simultaneously; while an IC chip is typically 5 x 5 mm, the beam itself can be 5 to 20 cm (full width measured at 90% max). The beam itself is typically Ar+ ions accelerated to 200 to 1200 eV with a current density of 0.1 to 1.5 mA/cm2. Using this technique, a chip can be etched to a specific device layer, imaged, etched to another device layer, imaged again, and so on, down to the device layer embedded into the silicon substrate. Imaging is usually low voltage or medium voltage scanning electron microscopy (SEM) because it has the resolution to see the device features, which can vary from several hundred nanometers on the topmost metallization layers down to tens of nanometers near the device layer. Additionally, elemental analysis can be used such as energy dispersive x-ray spectroscopy, known as EDX or EDS, or x-ray photoelectron spectroscopy (XPS). Optical images that look at whole device structure, while losing detail, are also common. This is a destructive technique, consuming the test chip. Figure 1 illustrates a typical structure of an IC. This image is a cross-sectional SEM image of a chip, produced by focused ion beam (FIB). Different chip architectures (memory, logic, power) will look distinct in their structure, but the fabrication techniques are the same: the chip is built layer by layer. The bottommost layer is the Si substrate, which can be 400 to 1200 µm in thickness (not shown). Using ion implantation through masks patterned by photolithography, individual transistors are defined. These can have feature sizes of a few nanometers up to 40 nm. Next, layer by layer and slowly increasing in size, conducting paths separated by insulating material are defined and deposited. The successive metal layers are connected by vertical channels called vias. Figure 2 exhibits the result from broad ion beam delayering a similar chip as shown in Fig. 1. Because it is etched top down across the area of the chip, this figure is in plan view. The chip was etched through several metal layers in one process step using Ar+ ions in a commercially available delayering system configured as described in this article. The etch was stopped near the beginning of the sixth metal layer from the bottom, designated M6, by observing the strength of the SIMS signal from the etched material over time (discussed below). Figure 2a, in color, is an optical image of the whole chip. It is overall copper colored as the conducting material is Cu, with an SiO2 insulator to isolate the traces. Figure 2b is an SEM image at 8 kV, a relatively low voltage, which allows viewing the metal traces with enough resolution to locate and image any defects. Additionally, Fig. 2c is taken at a higher voltage, 12 kV, and so the electrons from the column can penetrate deeper. The metal layer exposed on the surface, M6, is visible, as well as the layer underneath, M5. ION BEAM BENEFITS AND TRADEOFFS Ion sources were first developed to propel spacecraft before they were adapted for sputtering and etching. By accelerating the ions to extremely high velocities, the Fig. 2 An IC imaged after stopping the etch near the beginning of layer M6 (metal layer six) using ion beam delayering. (a) An optical image of the whole delayered chip. The high-level architecture can be seen. (b) and (c) Both are SEM micrographs, (b) at low voltage and (c) at high voltage. In the high voltage image, both M6 and the next layer down, M5, can be seen. Courtesy of TechInsights. (a) (b) (c) 10 µm 1 µm
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