edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 46 Whether networking at events or accessing information through EDFA, ISTFA proceedings, or journals, our members have the edge. Now it’s time to introduce EDFAS to others in the industry who would like to take advantage of these careerenhancing benefits. Help us help the industry by expanding our membership and offering others the same exceptional access to information and networking that sets EDFAS apart. To reacquaint yourself with and introduce others to the EDFAS member benefits, visit asminternational.org/web/edfas/membership. EDFAS MEMBERSHIP front side is being envisioned as a partial solution. Tools that can image in-between bulk silicon vias may have to be developed. Top challenges for packaging are summarized in Table 2. SUMMARY The FA future roadmap for the front end of the processing line foresees a need for atomic resolution with chemical species identification in a 3D volume bigger than 125,000 nm3 with nanometer area placement. Noninvasive sample preparation and imaging techniques will be needed for the metallization and inter-layer dielectic layer FA. For memory device FA, VNAND faces the hardest obstacles with no access to operating cells for fault isolation and difficult sample prep. In packaging, higher resolution and throughput of x-ray or x-ray like imaging of the package interconnect will be needed. Additionally, all areas of FA will require automation and will benefit from machine learning. Better discipline across functional areas and perhaps standardization of design for FA is going to become more critical as the fabless model continues to grow having been embraced by the world’s top semiconductor companies in providing and at the same time using this type of service. Table 2 Top challenges for packaging Area Challenges/gaps Gap analysis Imaging Noninvasive high resolution with high throughput. X-ray is currently limited, and no better alternatives are yet known. Improved resolution and throughput of x-ray imaging. New techniques. Thermal mapping 3D thermal mapping. External thermal mapping with sub-micron resolution. Signal analysis Package to die and die to package signal tracing. Combine node/layout information with package layout. Fault isolation and circuit edit Signal acquisition from backside with PowerVia and other bulk silicon vias. No known solution.
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