edfas.org 45 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 techniques). This means that they are either below the resolution limit of the current tool set or they are due to defects in the chemical composition or structure of materials. For the device front-end FA, we expect a growing need for FA tools to be able to provide atomic level resolution with 3D localization of species over a given volume (to be defined in this report). For established FA imaging tools, quantification of the images is a growing need and should be pursued by equipment manufacturers. For the back end, noninvasive imaging through a variety of materials must improve resolution and throughput. The era of quantum computing will require FA tools to operate at ultra-low temperature and new technologies to be invented or adapted. The transistor pathway is toward more vertical integration with the introduction of nanosheet gate all around (GAA) and following that the expected complementary FET with nMOS and pMOS stacked on top of each other. We introduce the concept of an analysis volume. To capture all the information that may lead to a root cause determination in a failing transistor, the volume to be analyzed with atomic level resolution must encompass an entire transistor structure. In the case of a GAA nanosheet, the gate length is about 10 nm as is the height. But these dimensions are multiplied three or four times in the vertical and lateral dimensions if the analysis is to include the source drain regions and part of the substrate. A minimum volume of 50 x 50 x 50 nm (125,000 nm3) will have to be analyzed with atomic-level resolution. This minimum volume is not expected to scale down because reductions in one dimension (lateral) will be offset by increases in another dimension (vertical) with the introduction of CFET and vertical TFET. Therefore, for the logic device front-end FA, this minimum volume must be analyzed with atomic-level resolution with chemical species identification. Other challenges include noninvasive sample prep and imaging of low-k films, even thinning and de-processing of metallization and ILD and high aspect ratio cross sectioning and imaging. The memory market is segmented into these three types of devices: volatile (dominated by DRAM), nonvolatile (dominated by vertical NAND, VNAND), and emerging (MRAM, RRAM, etc.). In the nonvolatile memory, density increase is achieved by growing vertically in the third dimension. Memory manufacturers are already at 176 layers and could grow to more than 512 layers by 2027. Two unique challenges in addition to the common ones facing FA of VNAND devices are sample preparation (cross-sectioning alignment to full VNAND stack) and physical access to cells while maintaining operation for fault isolation. There is currently a gap in the ability to evenly polish cross sections of VNAND devices. The other challenge has to do with the layout of the devices that are like stacked tree rings. The individual memory cells are inaccessible from the top of the circuit without destructive de-processing. For FA of a failing bit or bits, there is no known technique that can visibly access the cell components in the stack while maintaining operation. Top challenges for the front end are summarized in Table 1. In packaging, higher integration of chips/die per package and more layers of interconnect are expected to continue to grow. The introduction of PowerVia from Intel and other backside connectivity technologies being developed will further reduce access of the active circuitry through the backside. Critical FA tools rely on optical access to die from the backside for fault isolation, circuit edit, and root cause analysis. There is no known alternative to these backside techniques but access from the Table 1 Top challenges for front end Area Challenges/gaps Gap analysis Transistor module 3D transistor structures with stacked CMOS. Atomic level resolution imaging. Identification of species and location in 3D. Stoichiometric information. 3D memory Extreme aspect ratios and atomic level dielectric layer thicknesses. Inaccessible cells. Atomic level resolution of imaging. No identified solution for inaccessible cells while maintaining operation of device. Interconnect Very delicate low-k films. New metals (Co for example). Non-damaging imaging and sample prep techniques. Sample prep that can evenly remove materials of varying hardness.
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