edfas.org 41 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 follow the microscope manufacturer’s recommendations for operating the goniometer at high tilt angles. For more information, visit fischione.com. AVERY DESIGN SYSTEMS AND COMIRA PARTNER TO ENABLE UCIe-COMPLIANT CHIPLET DESIGN Avery Design Systems, a leader in functional verification solutions, and high-speed connectivity IP innovator CoMira Solutions announced a partnership aimed at enabling chiplet design using the UCIe (Universal Chiplet Interconnect Express) die-to-die interface standard. The combination of Avery’s verification IP (VIP) and functional verification platform and CoMira’s high speed protocol stack controller technology currently under development will provide an efficient approach to the design and verification of multi-die systems using the UCIe standard. Avery’s offering includes high quality models and test suites that support pre-silicon verification of systems using UCIe. UCIe was announced earlier this year as a way to provide interoperability of chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. The focus of the initial specification (version 1.0) covers the UCIe Adapter and PHY including die-to-die I/O physical layer, die-to-die protocols, and software stack which leverage the wellestablished PCI Express (PCIe) and Compute Express Link (CXL) industry standards in addition to a protocol-agnostic raw transfer mode. “CoMira is leveraging its extensive experience in highspeed connectivity IP to provide a reliable and easy-tointegrate UCIe protocol stack technology for multi-die systems. By supporting UCIe for connectivity within the chiplet architecture, and CXL and PCIe for external interfaces, we provide the necessary element for full chiplet connectivity,” says Qasim Shami, founder and CEO of CoMira Solutions. “Avery provides the ideal verification environment to allow pre-silicon validation for the entire chiplet system.” Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its UCIe offering supports standalone UCIe die to die adapter and LogPHY verification along with integrated PCIe and CXL VIP to run over the UCIe stack. In addition to UCIe models it provides comprehensive protocol checkers, coverage, reference testbenches, and compliance test-suites utilizing a flexible and open architecture. For more information, visit avery-design.com. SK HYNIX DEVELOPS WORLD’S FASTEST MOBILE DRAM SK hynix Inc. announces that it has developed the world’s fastest mobile DRAM LPDDR5T (low power double data rate 5 turbo) and provided sample products to customers. The new product operates at a data rate of 9.6 Gbps, 13% faster than the previous generation unveiled in 2022. The LPDDR5T, which operates in the ultra-low voltage range of 1.01 to 1.12V, set by the Joint Electron Device Engineering Council, is a product that not only features utmost speed but ultra-low-power consumption. SK hynix said it provided customers with samples of the 16 GB multi-chip package, which combines multiple LPDDR5T chips into one package. The packaged product can process 77 GB of data per second, which is equivalent to transferring fifteen full-HD movies in one second. Open chiplet platform on a package (HPCwire). SK Hynix low-power DRAM for mobile devices.
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