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A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2023 | VOLUME 25 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org WHOLE-CHIP DELAYERING FOR FA AND QUALITY ASSURANCE ARTIFICIAL INTELLIGENCE APPLICATIONS IN SEMICONDUCTOR FAILURE ANALYSIS EDFAS FAILURE ANALYSIS FUTURE ROADMAP FUNDAMENTALS OF CIRCUIT EDIT 4 16 9 44

A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2023 | VOLUME 25 | ISSUE 2 ELECTRONIC DEVICE FAILURE ANALYSIS edfas.org WHOLE-CHIP DELAYERING FOR FA AND QUALITY ASSURANCE ARTIFICIAL INTELLIGENCE APPLICATIONS IN SEMICONDUCTOR FAILURE ANALYSIS EDFAS FAILURE ANALYSIS FUTURE ROADMAP FUNDAMENTALS OF CIRCUIT EDIT 4 16 9 44

edfas.org 1 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 DEPARTMENTS Fundamentals of Circuit Edit David Akerson This article discusses the basics of focused ion beam (FIB) circuit edit and its benefits and provides tips to those new to circuit edit. Author Guidelines Author guidelines and a sample article are available at edfas.org. Potential authors should consult the guidelines for useful information prior to manuscript preparation. 4 9 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS MAY 2023 | VOLUME 25 | ISSUE 2 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS 2 GUEST EDITORIAL Felix Beaudoin, Renee Parente, and James Demarest 30 2023 PHOTO CONTEST 31 2023 VIDEO CONTEST 32 EDUCATION NEWS 33 UNIVERSITY HIGHLIGHT Konstantin Schekotihin 34 DIRECTORY OF FA PROVIDERS Rosalinda Ring 36 TRAINING CALENDAR Rosalinda Ring 38 LITERATURE REVIEW Michael R. Bruce 40 PRODUCT NEWS Ted Kolasa 44 GUEST COLUMN Nicholas Antoniou and Brendan Foran 48 ADVERTISERS INDEX Artificial Intelligence Applications in Semiconductor Failure Analysis Anna Safont-Andreu, Konstantin Schekotihin, Christian Burmer, Christian Hollerith, and Xue Ming Artificial intelligence can significantly change the way FA labs perform daily operations as well as increase impact on the global organizational level. 16 For the digital edition, log in to edfas.org, click on the “News/Magazines” tab, and select “EDFA Magazine.” Whole-Chip Delayering for Failure Analysis and Quality Assurance David Douglass and Kyle Godin Broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of unifor- mity coupled with the ability to precisely stop at the layer of interest enables repeatable, rapid whole-chip defect detection. 9 4 ABOUT THE COVER The metal short in this STEM image resembles a bull or buffalo with horns. Photo by Joshua Chang, Micron, First Place Winner in Black and White Images, 2022 EDFAS Photo Contest. 16

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Mary Anne Fleming Director, Journals, Magazines & Digital Media Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Space Systems Rosalinda M. Ring Thermo Fisher Scientific Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright © 2023 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $175 U.S. per year. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registered with the Copyright Clearance Center (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rosewood Drive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. 2023 marks the 25th anniversary of the ASM Electronic Device Failure Analysis Society (EDFAS). EDFAS was created to address the specific needs of our technical community. In 1998, the steering committee of the International Symposium for Testing and Failure Analysis (ISTFA) put forth a recommendation to the ASM Board of Trustees, and with their approval, EDFAS, a new ASM affiliate society, was formed. Today our society has more than one thousand members across all regions of the world. In addition to the ISTFA conference, the Society publishes this magazine and the EDFAS Desk Reference. The EDFAS board supports numerous committees including membership, educational, and technology roadmap committees. These engagements are only possible thanks to hundreds of volunteers like you who dedicate time and effort to create a society for sharing knowledge and exchanging ideas within our competitive industry. EDFAS strives to provide the knowledge and tools for our members to succeed in the field of failure analysis through a focus on three key strategic areas: ENGAGE: We commit to engaging with our members throughout the year by increasing the frequency of activities in addition to the ISTFA conference. For example, we have created an opportunity to meet virtually with experienced professionals through the speaker’s series. We also leverage the latest features of ASM Connect to help facilitate community discussions through the personalized discussion feed and quick access to EDFAS relevant items. EMPOWER: We support the development of technical content and ensure that it is broadly accessible in ASM Connect and in the ASM Digital Library. Our priority is to make certain that ISTFA remains the premier conference and exhibition for the global electronic failure analysis industry. We will endeavor to double our effort in the EDFAS technology roadmap initiative by collaborating with semiconductor and equipment manufacturing institutes. MAY 2023 | VOLUME 25 | ISSUE 2 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL WHAT’S EDFAS ALL ABOUT AFTER A QUARTER CENTURY? Felix Beaudoin, EDFAS President, GlobalFoundries felix.beaudoin@globalfoundries.com Renee Parente, EDFAS Vice-President, AMD renee.parente@amd.com James Demarest, EDFAS Immediate Past President, IBM jjdemar@us.ibm.com edfas.org Beaudoin (continued on page 48) Parente Demarest

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 4 EDFAAO (2023) 2:4-8 1537-0755/$19.00 ©ASM International® WHOLE-CHIP DELAYERING FOR FAILURE ANALYSIS AND QUALITY ASSURANCE David Douglass and Kyle Godin Denton Vacuum, Moorestown, New Jersey ddouglass@dentonvacuum.com INTRODUCTION As device features become smaller to keep up with Moore’s Law, fabrication processes must become more refined. All dimensions shrink and result in fabrication errors such as open circuits in conducting lines or vias. By imaging failed chips or test chips from the production line, regions of bad contact due to improper photolithography, nonuniform or nonconformal metal deposition, or voids, can be identified and corrected, increasing yield. There are several techniques that are commonly used for IC failure analysis, including focused ion beam (FIB), mechanical polishing, and chemical etching. The FIB uses a narrow ion beam to etch and must raster to perform an area etch. The time required makes it impractical to etch an entire IC. However, if a defect site is known in advance through electrical testing or x-ray imaging, then the FIB can drill down to the exact site and image the defect. Though it cannot perform whole-chip delayering, the FIB has the advantage of being able to etch a small area and repair a broken metal trace or via by depositing platinum atoms through a precursor gas that interacts with the ion beam. This leaves the rest of the chip untouched and functional. Most FIBs are integrated with an SEM for direct imaging of the process. Due to its special functions but inability to perform whole-chip delayering, the FIB and broad ion beam delayering are complementary techniques. Such is not the case for mechanical polishing or chemical etching, which promise to delayer the whole chip just as broad ion beam delayering does. Mechanical polishing requires a special test stand to make sure the chip is held at the correct orientation so that it delayers parallel to the planes of the layers and not at an angle. Because more polishing occurs at the leading edge of any mechanical system, so-called “dishing” is observed, which results is a small usable area. Additionally, it cannot be controllably stopped at a specific metal layer, rather it requires constant inspection and repolishing. Chemical etching is complex due to the broad variety of chemicals needed, which are different for each layer, and requires micropolishing steps to clean up the layers for good imaging. Common chemicals include HCl, FeCl3, H2O2, H2SO4, and polishing creams. Here broad ion beam delayering is preferred as it has superior uniformity, less process development than chemical etching, and can be controlled to stop at a specific depth by viewing the etch products in a mass spectrometer. The two key technical enablers of ion beam delayering are the broad beam ion source and secondary ion mass spectroscopy (SIMS). These will be discussed in more detail later in this article. The ion etch, being primarily a physical and not a chemical process, makes it possible to etch with low selectivity, resulting in highly planar removal Fig. 1 A FIB cross-section of a logic IC showing the stacked metal layers. Courtesy of TechInsights.

edfas.org 5 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 of layers containing both metal and dielectrics. The SIMS allows the etch to stop at a precise point during delayering rather than etching blindly. The metal layers closer to the device layer can be tens of nanometers in thickness, and SIMS has sufficient accuracy to stop the etch within a target layer. As a result, ion beam delayering enables users to understand the IC for failure analysis and quality assurance. Ion beam delayering uses a broad beam of ions from a gridded ion source to sequentially etch a whole integrated circuit (IC) chip from the top metal layer to the bottom device layer. The technique delayers the whole chip simultaneously; while an IC chip is typically 5 x 5 mm, the beam itself can be 5 to 20 cm (full width measured at 90% max). The beam itself is typically Ar+ ions accelerated to 200 to 1200 eV with a current density of 0.1 to 1.5 mA/cm2. Using this technique, a chip can be etched to a specific device layer, imaged, etched to another device layer, imaged again, and so on, down to the device layer embedded into the silicon substrate. Imaging is usually low voltage or medium voltage scanning electron microscopy (SEM) because it has the resolution to see the device features, which can vary from several hundred nanometers on the topmost metallization layers down to tens of nanometers near the device layer. Additionally, elemental analysis can be used such as energy dispersive x-ray spectroscopy, known as EDX or EDS, or x-ray photoelectron spectroscopy (XPS). Optical images that look at whole device structure, while losing detail, are also common. This is a destructive technique, consuming the test chip. Figure 1 illustrates a typical structure of an IC. This image is a cross-sectional SEM image of a chip, produced by focused ion beam (FIB). Different chip architectures (memory, logic, power) will look distinct in their structure, but the fabrication techniques are the same: the chip is built layer by layer. The bottommost layer is the Si substrate, which can be 400 to 1200 µm in thickness (not shown). Using ion implantation through masks patterned by photolithography, individual transistors are defined. These can have feature sizes of a few nanometers up to 40 nm. Next, layer by layer and slowly increasing in size, conducting paths separated by insulating material are defined and deposited. The successive metal layers are connected by vertical channels called vias. Figure 2 exhibits the result from broad ion beam delayering a similar chip as shown in Fig. 1. Because it is etched top down across the area of the chip, this figure is in plan view. The chip was etched through several metal layers in one process step using Ar+ ions in a commercially available delayering system configured as described in this article. The etch was stopped near the beginning of the sixth metal layer from the bottom, designated M6, by observing the strength of the SIMS signal from the etched material over time (discussed below). Figure 2a, in color, is an optical image of the whole chip. It is overall copper colored as the conducting material is Cu, with an SiO2 insulator to isolate the traces. Figure 2b is an SEM image at 8 kV, a relatively low voltage, which allows viewing the metal traces with enough resolution to locate and image any defects. Additionally, Fig. 2c is taken at a higher voltage, 12 kV, and so the electrons from the column can penetrate deeper. The metal layer exposed on the surface, M6, is visible, as well as the layer underneath, M5. ION BEAM BENEFITS AND TRADEOFFS Ion sources were first developed to propel spacecraft before they were adapted for sputtering and etching. By accelerating the ions to extremely high velocities, the Fig. 2 An IC imaged after stopping the etch near the beginning of layer M6 (metal layer six) using ion beam delayering. (a) An optical image of the whole delayered chip. The high-level architecture can be seen. (b) and (c) Both are SEM micrographs, (b) at low voltage and (c) at high voltage. In the high voltage image, both M6 and the next layer down, M5, can be seen. Courtesy of TechInsights. (a) (b) (c) 10 µm 1 µm

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 6 fuel efficiency of such a thruster is high. The ion source works by first producing a plasma, usually of chemically inert Ar atoms. This can be done through DC voltages or, more commonly for delayering applications, AC operating at radio frequency, 2 MHz or 13.56 MHz (Fig. 3). With the Ar atoms ionized to become charged Ar+ ions, they can be accelerated by a simple electric field. In practice, the acceleration is given by a circular plate with periodic holes (a grid). Due to the shape of the electric fields around the holes, over 95% of the accelerated ions pass through. A second plate, just behind the first, is grounded. This prevents the ions from being attracted back to the source. In such a gridded ion source the ion energy and the total beam current are decoupled, as the ion energy depends on the voltage applied to the grid while the current depends on the plasma density—via the gas density and RF power. A typical source runs at 200 to 1500 W RF power and 100 to 1500 V on the grids, accelerating the atoms to slightly less than 100 to 1500 eV. For perspective, an average atom at room temperature has 0.025 eV of kinetic energy. Gridded ion sources can be used for sputtering and thin film deposition by directing the ion beam at a target. Ion beam sputtering is preferred for some applications because, as the sputtering is a mainly physical rather than a thermal or chemical process, high temperature, refractory, or alloy material can be deposited. Also, the source and sputter plume are stable over tens of hours and thus it is preferred for the highest precision optical filters such as 100 GHz and 50 GHz DWDM filters for telecommunications. The ability to deposit high density alloys makes it preferred for data storage. In etch applications, where the beam is directed at the substrate, the ion beam can be uniform to a few percent over 300 mm and can etch any material. The same benefits above aid in IC delayering. As a physical process the etch selectivity is relatively low. Between hard and soft materials or different elements the etch rate may vary by a factor of two, compared to several orders of magnitude for chemical etch. ICs commonly contain Ta or W layers which the ion beam has no trouble with. The selectivity can be further tuned or reduced by changing the beam parameters (voltages), incidence angles, and by adding reactive gases to the plasma. The beam is broad, 5 to 20 cm in diameter, to improve the etch uniformity over the chip. The beam current density is greatest in the center and reduced at the edges, so to meet the uniformity requirements much of the beam is discarded and only a single or a few ICs are etched at a time, placed near the center of the ion beam. To achieve near zero selectivity on a complex, patterned IC consisting of many materials, some process development is required. Fortunately, for a typical IC metallization layer consisting of simply a metal and an insulator, a single parameter is all that is required to match the etch rates of the two materials. In practice, the process must be tuned for different chip architectures and different Fig. 3 A schematic of an ion source. Fig. 4 An IC delayering tool available from Denton Vacuum. (a) Shows an overview of the system consisting of a single wafer load lock, the sloped chamber in the center, and a process chamber. (b) Shows the inside of the process chamber. The ion source is to the left and the substrate is on a tilt and rotation stage in the center, with shutters currently closed. (c) Shows a better view of the source on the left, showing the grids themselves (grids from KRI). (a) (b) (c)

edfas.org 7 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 fabrication facilities, as material properties can change depending on how those thin films were deposited. An overview of a delayering tool is shown in Fig. 4. Figure 4a shows the tool itself, including a single wafer load lock and a process chamber. By minimizing pump down volume, the load lock reduces the analysis cycle time compared to venting the entire system for each chip. As the actual etch step takes a few to tens of minutes, it would be dominated by vacuum pumping and venting. In Fig. 4b the stage is in the center, complete with tilt, rotation, water cooling, and shutters. The ion source, to the left in 4b, is shown better in 4c. The source is 12 cm diameter. Etch selectivity can be controlled through several methods. The physical sputtering process, by which the chips are etched, is not trivial to model and is captured in the single parameter called the “sputter yield.” Sputter yield is the average number of substrate atoms kicked out per incident atom. This is a mainly physical process, like “bowling with atoms.” Sputter yields vary from 0.5 to 2. The sputter yield is dependent on several factors including the materials, both gas and etch material, the ion energy, and the angle of incidence of the ion to the surface. None of these trends are easily predictable for a given material, and do not follow simple equations. Adding reactive gases such as O2 to the source can provide further control. The result is that, since different materials follow different trends, by only changing one or two parameters, such as the tilt and beam voltage, two materials sputter yields (etch rates) can be matched. An example of this is shown in Fig. 5. In Fig. 5, an experiment was run by keeping the beam voltages, currents, RF power, and gases all constant while only changing the incidence angle. The etch rate was measured by looking at the mass spectrometer signal strength after calibrating with a test etch sample. At incident angles below 70 degrees, the etch rate of the soft Al film is higher. At angles above 70 degrees, the etch rate of the SiO2 is higher. Thus, there is a sweet spot around 70 degrees where the etch rates are matched and the selectivity drops to zero. This experiment was performed with separate thin films, but it has been observed that the architecture of the chip can affect the result (the ratio of Al to SiO2 as well as linewidths). SECONDARY ION MASS SPECTROSCOPY When an energetic ion impinges on a solid surface, atoms from the surface are ejected or sputtered. A fraction of these ejected atoms are also ionized. These socalled “secondary ions” contain information about the elemental, isotopic, and molecular composition of the surface. Secondary ion mass spectroscopy uses a quadrupole mass spectrometer to measure the masses of ions entering the instrument (Fig. 6). Depending on the mass and charge of the ions entering the electric and magnetic fields, their trajectory will be deviated greater or less. Some will be collected by the detector and most rejected. By scanning the voltages and currents in the device, a full spectrum of signal versus mass can be collected. A typical device on the market can scan 0 to 300 AMU in less than a second and has a working range from 50 counts per second (limited by noise) up to 107 counts per second. Fig. 5 Etch rate of SiO2 and Al thin films as incidence angle (tilt) is changed. At around 70 degrees incidence, the etch rates are the same and selectivity drops to zero. Gas, beam currents, and voltages are constant in the experiment. Fig. 6 An illustration of an ion source etching a substrate and ions being collected by the SIMS.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 8 SIMS is critical to broad ion beam delayering because it enables the etch to be stopped on a specific layer. As the substrate is etched, a time series is produced containing the signal from different masses corresponding to the expected etch products (Cu, Al, Ta, W). Si from Si or SiO2 is difficult to observe because the peak, at 28 AMU, overlaps with background N2, which is a stronger signal. An example trace is shown in Fig. 7a, with a cross section of a chip of the same design shown in 7b. As the ion beam etches the chip, from top to bottom in Fig. 7b, the time series is produced showing a periodic rise and fall of the Cu signal from the metal layers and the Ta signal from the vias. In this case, the whole chip was etched to produce this time series. However, the SIMS signal can be used to stop at a precise point. For instance, knowing that the chip has seven metal layers that are all Cu, one can pre-program the tool to stop at the third rise of the Cu signal, corresponding to M5. The chip can then be removed, imaged at M5, and then placed back for further delayering. An example of this is shown in Fig. 7c, where the second rise is identified as the stop point. CONCLUSION As demonstrated above, broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of uniformity coupled with the ability to precisely stop at the layer of interest enables rapid wholechip defect detection. Because this is a fully computercontrolled process with SIMS endpoint detection, the process is completely repeatable from device to device and technician to technician. ABOUT THE AUTHORS David Douglass has a B.S. in engineering physics and a Ph.D. in physics from the University of Virginia. He has many years of experience in laser development, as well as technical marketing for capital equipment in photonics and semiconductor applications. He is currently at Denton Vacuum, managing both applications development and technical marketing. Kyle Godin graduated with a B.S. in physics from Rose-Hulman with a specialization in semiconductor devices, an M.S. in microelectronics-photonics from the University of Arkansas, and Ph.D. in interdisciplinary engineering from Stevens Institute of Technology. After doing research in 2D materials and photonics, doing end-to-end fabrication and characterization of simple devices, he has worked in ion beam sputtering and ion sources for five years. He is currently at Denton Vacuum in Moorestown, New Jersey. (a) (b) (c) Fig. 7 SIMS signals and end points. Advertise in Electronic Device Failure Analysis magazine! For information about advertising in Electronic Device Failure Analysis: Kelly Johanns, Business Development Manager 440.671.3851, kelly.johanns@asminternational.org Current rate card may be viewed online at asminternational.org/mediakit.

edfas.org 9 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 FUNDAMENTALS OF CIRCUIT EDIT David Akerson Thermo Fisher Scientific, Hillsboro, Oregon david.akerson@thermofisher.com EDFAAO (2023) 2:9-13 1537-0755/$19.00 ©ASM International® INTRODUCTION For semiconductor manufacturers, accelerating product development and time-to-market are critical, as missing a technology window, or falling behind, can result in significant loss of revenue. Increased densities, smaller features, complex device designs, and advanced packaging make it more likely that first silicon will not function as intended. As semiconductors become more complex, the circuit edit function continues to grow in strategic importance for reducing development costs, improving performance and functionality, and accelerating time to market. FIB CIRCUIT EDITING AND BENEFITS Focused ion beam (FIB) chip circuit editing is a wellestablished technique that enables the direct repair of integrated circuit defects. A precisely tuned and accurately placed ion beam with nanoscale resolution, in conjunction with process gases, selectively uncovers internal circuitry, allowing a skilled FIB operator to make functional changes to the device or the copper wiring pattern (Fig. 1). The FIB operator then reseals the chip surface to produce a device with revised circuit logic functions. For the integrated circuit (IC) developer and the IC company, circuit edit enables several benefits. For IC developers, FIB circuit editing enables debugging and validating fixes, exploring design optimization changes, duplicating and scaling pre-production parts, and prototyping new devices. These prototypes support the product and platform development efforts of internal teams, such as software and firmware, validation, and manufacturing to keep projects on schedule. Externally, functional prototypes can support ecosystem enablement and end customer design-in activities. For the IC company, circuit edit provides the ability to eliminate unnecessary wafer costs and accelerate time-to-market. The remainder of this article is a starting point for engineers and scientists who would like to learn more about circuit edit or are just starting their career in circuit edit. But be forewarned, becoming an “expert” practitioner takes time and practice. The good and bad news is, nobody, not even “expert” practitioners, have a 100% success rate. BUILDING THE UNDERLYING SKILLS Successful circuit editing is built upon two skills: proficiency with ion beam technology and an understanding of the chemistries that can be applied using a gas injection system (GIS). An understanding of circuit layout and the structure of ICs is also needed as explained below. Readers coming into this with experience in one area, both areas, or neither will find adding GIS knowledge to FIB, or vice versa, is relatively straightforward. Fig. 1 The circuit edit system enables direct access to each layer. From left to right: N-well, FinFET/Poly, metal, and contact/via.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 10 If one is new to both, start with FIB because it’s the key to pinpointing, imaging, and manipulating the target area to be edited. Next, develop proficiency with the positioning of gas nozzles and the application of the necessary chemistry. GETTING STARTED When preparing to sit down and start a circuit-edit session, it is critical to be familiar with device technology, process, and validation. This includes the structure of each device, including: the number of metal layers, the technology nodes, and the cross section. It is also useful to know the electrical equivalent circuits and the preferred test methods for the target device. Below are three keys for increasing the odds of a successful circuit edit: 1. Get familiar with the circuit-edit solution: Precision, efficiency, and success are more likely when familiar with the capabilities of the circuit-edit solution, including basic capabilities, advanced features, and everything in between. Mastery of the basics serves an essential foundation for precise surgery on advanced devices. Next-level mastery adds the ability to identify which situations are best addressed by one or more of the special features of the instrument. For example, the availability of lower beam energy helps minimize the chances of destroying sensitive circuits (or even the sample itself) during the edit process. 2. Understand the circuit layout: Circuit layout is specific to each device, and it is important to prepare as much as possible. For example, it is imperative to know which circuit elements are sacrificial: silicon capacitors, buffers, input/output (I/O), ring oscillators, etc. These elements can also provide reference points as the editing process progresses; sacrificial devices (i.e., disposable samples) are often exposed (via milling or trenching) to establish reference points within the computer-aided design (CAD) layout to ensure precise alignment. It is therefore critical to know what can be exposed without altering or destroying device functionality. It is also important to know which layers the FIB can access and connect to, such as metal 0, metal 1, and contacts. This is easier if the device has been designed with FIB in mind, but this is unfortunately not a universally accepted practice. In many cases, it is best to acquire the correct CAD data and develop an edit scheme in collaboration with the circuit designer. They will be able to identify the signals of interest and point out which, if any, obstructing metal lines can be cut. 3. Remember a few basics: Before embarking on the editing process, it is useful to remember four key fundamentals: • Create a circuit-edit plan and clearly state the goal of the editing process. If the realities of the target location make it difficult to perform circuit editing, meet with the designer or a test engineer and discuss the electrical equivalent circuit. Then, before starting the actual work, clarify and refine the edit plan and the goal. • Always wear gloves when handling the device and any of the editing system’s vacuum parts. • Review and understand the best-known method (BKM) for setting up the target device. • Know how to insert unique packaging, and then mount the device to ensure it is well grounded. Avoid electrostatic build up when handling and operating on the device. THE GENERAL WORKFLOW Circuit editing begins with sample preparation. Naturally, if the device is no longer intact after this step, no amount of circuit editing can revive it into a functional device. Whether it’s backside or frontside editing, begin by decapping the package. For backside editing, the next step is grinding and polishing of the device. For frontside editing, the next step is removal of the polyamide layer. Next, global alignment is performed via CAD layout. For backside editing, the initial alignment is accomplished by using the IR camera to identify features and an optical image is then calibrated to the CAD layout. In the case of frontside editing, the FIB is used to image fiducials on the surface. The FIB is then aligned to the CAD layout. Both of these can be achieved using specialized CAD tools from a variety of vendors. The next steps apply to every location that requires circuit editing, with some variation between backside editing (e.g., bulk silicon trenching) and frontside editing (e.g., delayering). BULK SILICON TRENCHING, DELAYERING, REVISING LINES, AND REFILLING PLUS INSULATING With backside editing, trenching is used to access the layer or line to be edited. The key parameters are box size, application file, chemistry, beam current, and contrast setting. When performing backside editing, it is also important to review the workflow for backside silicon (Si) trenching:

edfas.org 11 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 • Measure the silicon thickness with IR • Validate the etching rate • Initiate backside trenching at the validated etching rate During trenching, uniform gas distribution is essential to ensuring even and predictable detection of the N-well. The moment that the N-well appears, it is critical to stop etching any further. Stand-alone trenching systems using laser assisted chemical etching are also available and can significantly speed up the backside editing process. In frontside editing, delayering via the top layer is used to access the underlying layer or line to be edited. The key parameters to consider are box size, application file, chemistry, and beam current. Next, specific lines are cut (if needed), and/or new lines are deposited. Certain lines are also extended to create test points or probing leads. This stage may also require the milling of vias within a layer or between layers. Key steps for revising lines include: • Performing local alignment and navigation to the region of interest • Using delayering to access the target layers • Initiating the final alignment process before cutting, positioning, and editing the line This work is made easier with a circuit-edit solution that enables milling of vias with high aspect ratios and provides precise visualization and detection of endpoints. Finally, material is deposited to refill the N-well trench and to insulate, or isolate, the edited area. An example of this process is the filling of vias. It also should be noted, insulator deposition is critical to passivate any exposed silicon and metal lines. For instance, XeF2 can unintentionally etch exposed silicon if applied. Iodine chemistry, typically reserved for silicon, SiO2, or aluminum etching, causes copper to corrode. A good practice is to ensure that anything that has been exposed gets covered to prevent unintended corrosion. It is also suggested that new practitioners write down their workflow on a whiteboard within eyeshot of their circuit-edit system. STARTING POINTS FOR SPECIFIC PARAMETERS AND BEST CHEMISTRIES After getting comfortable with the relevant workflows, one can get more specific. A few key parameters at the top of the list are: box size; minimum, maximum, and optimum current; and minimum, maximum, and optimum beam energy. Start by reviewing the particulars of the process node, the relevant cross-sectional information, and the constituent materials. From there, one can more easily define the best box size for the circuit edit before getting down to work. It is critical to understand the material composition of a device, as the right choice of beam chemistry can enhance the speed, efficiency, and precision of etching/ milling operations. Key questions to ask are: • Which chemistries work best with the materials in the device (Table 1)? • Which chemistries are incompatible with those materials? To help avoid potential problems, the following combinations require all due caution and attention: 1. Insulator enhanced etch with xenon difluoride (IEE XeF2) spontaneously etches silicon and also accelerates removal of SiO2 layers. Consequently, it should be used carefully when performing backside editing through silicon structures. Another IEE process benefit is that it Table 1 Common combinations of chemistries and materials Etching beam chemistry Action and target material Insulator enhanced etch with xenon difluoride (IEE XeF2) Backside etch of SiO2, Si Enhanced etch with diiodine (EE I2) Backside trench floor of Al, shallow Si Selective carbon mill with water (SCM H20) Mill thick Cu on SiO2, polyamide Delineation etch (DE) Expose tungsten and remove low-K dielectric DX chemistry Etch Cu on low-K dielectric THE MOMENT THAT THE N-WELL APPEARS, IT IS CRITICAL TO STOP ETCHING ANY FURTHER.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 12 generally etches insulators faster than conductors, leaving the underlying metal contact lines intact (Fig. 2). 2. Enhanced etch with diiodine (EE I2) accelerates the removal of aluminum (Al) layers, but it also corrodes copper (Cu) layers. As a general note, Cu should not be exposed to iodine. When applying chemistries, nozzle location is important (Fig. 3). In practice, the best choices vary by application. As a general note, gas nozzles should be placed farther away from the region of injection if greater contrast is needed. One reason: close placement can hinder the production of secondary electrons and reduce image quality. Careful consideration of four more parameters will enhance success rate: 1. Finding the proper ratio between oxygen and the insulator deposition (IDEP) chemistry 2. Optimizing the ratio of oxygen source (e.g., O2 or H2O) and the precursor 3. Establishing the right flow rate, neither too much nor too little 4. Optimizing pixel density and dwell time to maximize image resolution As a rule of thumb, the smallest possible dose is best and it should be noted refresh rate, retrace times, and raster pattern times should be taken into consideration. ESSENTIAL FIB PARAMETERS When working with a FIB-based circuit-edit system, the key factors are beam current, GIS chemistries, imaging parameters, and end points. These key factors are determined based on the patterning parameters of pixel density, thickness, visible end-pointing, and graphical end-pointing. A FRAMEWORK FOR KNOWING WHEN TO STOP Knowing when to stop depends on tool capability, user experience, and advice from device experts. For example, what is the right depth for an N-well for a given process, device, or architecture? Graphical end-pointing can help determine when to stop during small via edits. In terms of user experience, this is where it becomes necessary to turn science into art. Mastering the “art” certainly comes with practice. The “science” requires gaining familiarity with the end-point detection system built into systems (Fig. 4). The detection system provides a visual indicator of what’s happening by measuring the secondary electrons that are emitted from the edited material. Note that SiO2 Fig. 3 Precise chemistry delivery is essential to making exact cuts and achieving uniform delayering, and the use of advanced gas-injection systems ensures optimal interaction of the chemistry, the beam, and the device. Fig. 2 The IEE process generally etches insulators faster than conductors, leaving the underlying metal contact lines intact. Fig. 4 Art and science meet to create an N-well with the right depth.

edfas.org 13 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 makes circuit edit and the ability to deliver a functional device in a timely fashion very valuable to an organization. SUGGESTED REFERENCES 1. C. Park, et al.: “FIB Overview,” Microelectronics Failure Analysis: Desk Reference (Seventh Edition), ASM International, 2019, https://doi. org/10.31399/asm.tb.mfadr7.t91110335. 2. M. DiBattista and T.R. Lundquist: “Role of Advanced Circuit Edit for First Silicon Debug,” Microelectronics Failure Analysis: Desk Reference (Seventh Edition), ASM International, 2019, https://doi.org/10.31399/ asm.tb.mfadr7.t91110351. 3. K.A. Serrels and U. Ganesh: “Laser Voltage Probing of Integrated Circuits: Implementation and Impact,” Microelectronics Failure Analysis: Desk Reference (Seventh Edition), ASM International, 2019, https://doi.org/10.31399/asm.tb.mfadr7.t91110244. has few secondary electrons, but metals such as copper and aluminum have many. Consequently, the transition between materials appears as a step function in the emission-level graph. When milling through an insulator, there will be an upward step when a metal line or layer is reached. When cutting through a metal line or layer, there will be a downward step when the cut is complete. CONCLUSION For circuit edit practitioners, it is a very exciting time, and it is expected that the circuit edit function will continue to grow in strategic value. As devices and manufacturing processes become more complex with more steps, the probability of functional defects becomes higher. This ABOUT THE AUTHOR David Akerson is a senior global market development manager in Thermo Fisher Scientific’s Semiconductor Business and has over 20 years of product management and marketing management experience in the semiconductor industry. NOTEWORTHY NEWS FIB SEM MEETING 2023 The 15th annual FIB SEM Meeting will be held June 11-16, in conjunction with IUMAS 8 in Banff, AB Canada. FIB SEM will feature presentations, tutorials, and posters by FIB users and vendors, highlighting new applications and the latest technology. The event offers plenty of technical content as well as opportunities for informal discussions with your FIB colleagues. FIB SEM 2024 will be held back in the Maryland/DC area. For more information, visit fibsem.net or email keana.scott@nist.gov. IPFA 2023 The 30th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) will be held in July 2023 in Penang, Malaysia. The event will be devoted to the fundamental understanding of the physical characterization techniques and associated technologies that assist in probing the nature of wearout and failure in conventional and new CMOS devices, in turn resulting in improved know-how of the physics of device, circuit, and module failure that serves as critical input for future design and reliability. The symposium is technically cosponsored by the IEEE Electron Device Society and IEEE Reliability Society. For more information, visit the IPFA website at ipfa-ieee.org.

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edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 16 ARTIFICIAL INTELLIGENCE APPLICATIONS IN SEMICONDUCTOR FAILURE ANALYSIS Anna Safont-Andreu1, Konstantin Schekotihin2, Christian Burmer3, Christian Hollerith3, and Xue Ming4 1Infineon Technologies AT, Villach, Austria 2Alpen-Adria-Universität, Klagenfurt, Austria 3Infineon Technologies AG, Munich, Germany 4Infineon Technologies Asia Pacific Pte Ltd, Singapore konstantin.schekotihin@aau.com EDFAAO (2023) 2:16-28 1537-0755/$19.00 ©ASM International® INTRODUCTION Over the decades, semiconductors have become very complex devices appearing in all spheres of life. Growing complexity poses a significant challenge for further research, development, fabrication, and after-sales support of these devices. It is widely recognized that artificial intelligence (AI) has a huge potential to solve many issues in the industry and generate vast business value. A recently conducted survey of semiconductor executives indicates that about 77% of companies are adopting AI in their businesses, and among them, about 63% expect AI to have a crucial impact on their businesses being a key approach to mitigate fast-rising expenses for each new technology step, such as the transition from 7 nm to 5 nm process.[1] In particular, semiconductor manufacturers plan to increase productivity in all activities using AI techniques. According to McKinsey,[2] at the moment, AI is used to only 10% of its potential within the industry. Utilization of its full capabilities might increase the added value to annual company earnings from the current $5–$8 billion to $85–$90 billion per year. Among the critical contributions of AI, the report highlights aspects of failure analysis (FA), such as defect identification/prediction and automation of deviation handling, as well as automated testing and root cause analysis. FA supports design, prototyping, manufacturing, and after-sales operations of a semiconductor company by providing identification and localization of root causes for the electrical malfunction of devices, performing quality and robustness analysis, or executing production control. In all these stages, fast and precise feedback from an FA lab is essential for their successful completion. As a result, FA activities bring much value to the whole semiconductor company (Fig. 1). However, all FA activities are very knowledge-intensive and quite tedious as they require an engineer to have a deep understanding of physical processes, possess all relevant information about the device, and be aware of best practices and common failure patterns appearing in images and measurements gained from previous analyses. Although modern AI methods cannot replace an FA engineer, they can significantly reduce the load by automating many of the time-consuming tasks like recognition of failure patterns, search and retrieval of information about devices, or scheduling of FA jobs and tools to engineers. Fig. 1 Value added by FA to the life cycle of semiconductor devices.

edfas.org 17 ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 This article provides a systematic overview of AI methods relevant to the FA domain aiming to guide researchers and practitioners in this area. Specifically, the authors follow a classic view on AI, discriminating between knowledge-based and machine-learning approaches. The former makes decisions using efficient reasoning systems with knowledge explicitly provided by experts and stored in knowledge bases. In contrast, machine learning methods acquire all knowledge required to make decisions inductively from (annotated) data. The literature survey shows that both AI approaches have their pros and cons for FA applications, focusing on the works published in the last years and covering a wide spectrum of topics including various diagnostic stages, predictive analytics, manufacturing-oriented FA tasks, or counterfeit verification. Finally, a short overview of the most representative AI methods and outline future applications of AI in the FA domain is provided. ARTIFICIAL INTELLIGENCE Artificial intelligence is a multidisciplinary science that unites computer science, mathematical logic, philosophy, probability, control and information theories, statistics, and many others. Since the early 1940s, with the development of digital electronic computers, mathematicians, engineers, and computer scientists have started to explore possibilities for the creation of intelligent machines. In 1950, Alan Turing suggested one of the first known intelligence tests known as the “Turing test,” which aims to classify machines into intelligent and not.[3] The term “artificial intelligence” was suggested by John McCarthy during a workshop held in 1965 at Dartmouth College.[4] In modern literature, for example reference 5, there are four various definitions of AI, which can be summarized as follows: Thinking humanly. Focus on activities associated with human thinking, like problem-solving, learning, or decision-making.[6] Acting humanly. Create machines performing functions that require human-level intelligence.[7] Thinking rationally. Research computations enabling a machine to perceive, reason, and act.[8] Acting rationally. Concerned with intelligent behavior in artifacts.[9] The first two definitions represent different perspectives on strong AI, also known as artificial general intelligence, capable of (nearly) human intelligence. However, after decades of research, it became clear that the initial dream of a strong AI is hard or even impossible to reach with modern technology. Therefore, researchers and practitioners are mostly focusing on the methods following the last two AI definitions, which are often referred to as weak or narrow AI. Methods of this family aim to solve a specific task, such as answering questions or recognizing objects on an image, and rely on the human ability to analyze the application domain in order to collect data, define models capturing knowledge about the domain, or determine training and reasoning procedures. There are many different classifications of weak AI methods, which differentiate between them, e.g., by applied decision-making approaches or required data. For FA applications, we classify methods by the approaches they are using to acquire and use knowledge about the domain. In particular, we differentiate between symbolic and machine-learning methods, as shown schematically in Fig. 2. The former acquire the knowledge deductively, i.e., directly from experts, who analyze the problem and use some formal language to encode their knowledge in a machine-readable form. Next, this knowledge is used by algorithms to find a solution to a problem. In turn, machine learning methods, as the name suggests, create models representing domain knowledge inductively, i.e., directly from (annotated) data. Let us exemplify these introduced notions using two FA-relevant problems, using Fig. 3 to illustrate the discussion. Symbolic approach. Consider a simple scheduling problem of an FA lab: given three sets of engineers, machines, and jobs, where every job is represented by a sequence of tasks; find an assignment of tasks to engineers and machines, such that the total processing time of all jobs is minimized. Experts can easily formulate requirements to a schedule, e.g., Fig. 2 General classification of AI methods.

edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 25 NO. 2 18 all tasks are non-preemptive or some tools can be used to execute only one task at a time. All these requirements, encoded in a machine-readable form using languages of constraints or mixed integer programming, are stored in a knowledge base. Every time a schedule must be computed, e.g., a new job arrives or a tool/engineer is idle, the system automatically generates an instance comprising the updated sets of jobs, tools, and engineers. Next, the instance is provided together with the knowledge base to a solver, and intelligent algorithms find a schedule. Machine learning approach. The main issue with the simple scheduling problem above is that an arbitrary FA job cannot be easily represented as a sequence of tasks. In many cases, the next task in a sequence is defined by the findings of an engineer while executing previous ones. Because there are many different special cases, experts are unable to list them all in a knowledge base and maintain this list over time. Instead, an expert uses machine learning methods to acquire this knowledge directly from data. Nevertheless, the application of such methods cannot be done completely automatically. Experts must use their knowledge about the domain to collect representative data describing various jobs, define a learning method and its objectives, and execute the training procedure. Given an observation comprising a sequence of tasks and data recorded during their execution, a trained model predicts the next task in the sequence. In addition, for many machine learning approaches experts must annotate the data with labels indicating the required outputs of a model. The annotation process might be quite costly, but it enables an additional knowledge transfer from experts to an AI system and, thus, often results in a better performance of trained models. Hybrid. As can be seen from the examples above, both approaches must be combined in a hybrid one to solve real-world problems appearing in the FA domain. However, the creation of such hybrid systems is still a field of active research[10] and, therefore, it is hard to give their systematic overview. Nevertheless, in the remainder of the paper, we provide hints about their possi- ble applications. SYMBOLIC METHODS One of the main hypotheses behind the symbolic methods assumes that any intelligent system represents and reasons about the world using symbols.[11] This family of methods originates in the attempts of Ancient Greece philosophers to establish laws of thought by formalizing principles of human reasoning. Thus, the syllogisms of Aristotle provided rules allowing for the derivation of correct conclusions out of correct premises. These rules showed that human decision-making can be automated, thus, initiating the study of logic. Over the centuries, logicians turned this field into a mathematically founded study of knowledge representation and reasoning, which ended up in the development of computer systems in the late 1960s that could, in principle, solve any problem represented in logic notation.[12] In the next two decades, a pure logicist approach to symbolic AI was extended with the development of heuristic search methods to create expert systems.[13] Equipped with encoded knowledge and powerful heuristic search algorithms, Deep Blue was able to beat Garry Kasparov in 1996. However, soon it was realized that the maintenance of large knowledge bases and logic-based reasoning differentiating only between true and false statements is insufficient to solve many real-world problems. Therefore, researchers started to extend symbolic methods with methods able to handle uncertainty, like fuzzy logic[14] or probabilistic reasoning,[15] as well as with learning capabilities, like version Fig. 3 Sample workflows of AI methods.

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