edfas.org 29 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 (continued on page 32) attempts, the substrate is thinned, causing the capacitance of the TSV to decrease. This change in capacitance can be detectedby a control unit in the target chip.[17] This designbased solution is relatively robust for electrical probing attacks. However, this solution will not be effective with other imaging modalities that do not require any sample preparation. Apackagingmethodwas proposed inReference18 that comprises of a backside shield with deeply-etched blind holes and a metal lining. The etched holes weaken the chip, leading to damage if mechanical stress is introduced from polishing or plasma focused ion beam (FIB). CONCLUSION This article described how physical attacks can be launched on different types of contemporary and emerging nonvolatile memory cells, using advanced state-ofthe-art FA tools. The bit information stored inside an NVM device cell can be subjected to read-out or fault injection attacks. We investigated the security vulnerabilities of emerging nonvolatile memory cells to these nondestructive physical attacks. Additionally, we have defined multiple types of vulnerability parameters to help quantify and formulatemetrics. We clearly defined amethodology, along with examples, to establish vulnerability metrics against different imaging and fault injection modalities used for physical attacks. Finally, we put forth an in-depth security analysis of the different emerging NVM technologies, alongwith adiscussiononpossible countermeasures at different levels. REFERENCES 1. https://www.mordorintelligence.com/industry-reports/non- volatilememory-market. 2. N. Asadizanjani, M.T. Rahman, andM. Tehranipoor: Physical Inspection and Attacks: An Overview. Cham: Springer International Publishing, 2021, p. 1–20, https://doi.org/10. 1007/978-3-030-62609-9{\_}1. 3. D. Richter: Flash Memories, Springer, 2016. 4. J.S. Meena, et al.: “Overview of Emerging Nonvolatile Memory Technologies,” NanoscaleResearch Letters, 2014, Vol. 9, No. 1, p. 1–33. 5. W. Banerjee: “Challenges and Applications of Emerging Nonvolatile Memory Devices,” Electronics, 2020, Vol. 9, No. 6, p. 1029. 6. A. Chen: “A Review of Emerging Non-volatile Memory (nvm) Technologies and Applications,” Solid-State Electronics, 2016, Vol. 125, p. 25–38. 7. T. Mikolajick, et al.: “Ferroelectric Hafnium Oxide for Ferroelectric Random-accessMemories and Ferroelectric Field-effect Transistors,” MRSs Bulletin, 2018, Vol. 43, No. 5, p. 340–346. 8. M. Moore: “International Roadmap for Devices and Systems,” 2017. 9. S. Skorobogatov: “LowTemperatureData Remanence in Static Ram,” University of Cambridge, Computer Laboratory, Tech. Rep., 2002. 10. J.J. Fournier and P. Loubet-Moundi: “Memory Address Scrambling Revealed using Fault Attacks,” 2010Workshop on Fault Diagnosis and Tolerance in Cryptography, IEEE, 2010, p. 30–36. 11. N. Rangarajan, et al.: “Tamper-proof Hardware from Emerging Technologies,” The Next Era in Hardware Security, Springer, 2021, p. 195–209. 12. M. Rostami, F. Koushanfar, and R. Karri: “A Primer on Hardware Security: Models, Methods, and Metrics,” Proceedings of the IEEE, 2014, Vol. 102, No. 8, p. 1283–1295. 13. C. Chavda, et al.: “Vulnerability Analysis of {On-Chip}{Access-Control} Memory,” 9th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage 17), 2017. 14. H. Shen and D. Forte: “Nanopyramid: An Optical Scrambler Against Backside Probing Attacks,” 2018. 15. J.-D.V. Hoang, et al.: “Breakthrough Packaging Level Shielding Techniques and EMI Effectiveness Modeling and Characterization,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), IEEE, 2016, p. 1290–1296. 16. W. Xiong, et al.: “Analysis of Electromagnetic Shielding of IC Package with Thin Absorbing Material Coating Inside in Two Different Configurations,” 2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), IEEE, 2018, p. 1216–1221. 17. S. ManichBou, et al.: “Backside Polishing Detector: ANewProtection Against Backside Attacks,” in DCIS’15-XXX Conference on Design of Circuits and Integrated Systems, 2015. 18. S. Borel, et al.: “A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SIP,” 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), IEEE, 2018, p. 515–520. ABOUT THE AUTHORS Liton Kumar Biswas is currently a Ph.D. student at the University of Florida in the electrical and computer engineering department. He received his B.S. andM.S. degrees in applied physics, electronics, and communication engineering in 2010 and 2011, respectively, from the University of Dhaka. His research is focused on finding vulnerabilities using physical inspection, hardware security and assurance, and reverse engineering. M. Shafkat M. Khan is currently a Ph.D. student at the University of Florida in the electrical and computer engineering department since Spring 2021. He received an B.S. degree in electrical and electronic engineering from the Bangladesh University of Engineering and Technology (BUET) in 2019. His research is focused onmulti-die packaging security and trust, physical inspection, and attacks.
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