edfas.org 21 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 REFERENCES 1. U.S. Department of Commerce, “Defense Industrial BaseAssessment: Counterfeit Electronics,” January 2010, https://www.bis.doc.gov/ index.php/documents/technology-evaluation/37-defense-industrial-base-assessment-of-counterfeit-electronics-2010/file, p. 2-5. 2. Semiconductor IndustryAssociation, “Stateof theU.S.Semiconductor Industry,” July 2020, https://www.semiconductors.org/wp-content/ uploads/2020/07/2020-SIA-State-of-the-Industry-Report-FINAL-1. pdf, p. 9-15. 3. S.M.S. Trimberger: “Three Ages of FPGAs: ARetrospective on the First Thirty Years of FPGA Technology: This Paper Reflects onHowMoore’s LawHas Driven the Design of FPGAs Through Three Epochs: The Age of Invention, the Age of Expansion, and the Age of Accumulation,” IEEE Solid-State Circuits Magazine, 2018, Vol. 10, No. 2, p. 16-29. 4. F. Koushanfar: “HardwareMetering: A Survey,” ed. byM. Tehranipoor and C. Wang, Springer, 2012. 5. B. Gassend, et al.: “Silicon Physical RandomFunctions,” Proceedings of the 9thACMConference onComputer andCommunications Security, 2002, p. 148-160. 6. P. Kocher, J. Jaffe, andB. Jun: “Differential Power Analysis,” Advances in Cryptology — CRYPTO’ 99, ed. by Michael Wiener, Springer Berlin Heidelberg, 1999, p. 388–397. 7. U. Rührmair, S. Devadas, and F. Koushanfar: “Security Based on Physical Unclonability andDisorder,” ed. byMohammadTehranipoor and Cliff Wang, Springer, 2012. 8. M. Rostami, F. Koushanfar, and R. Karri: “A Primer on Hardware Security: Models, Methods, and Metrics,” Proceedings of the IEEE, 2014, p. 1283–1295. 9. J. Guajardo, et al.: “FPGA Intrinsic PUFs and Their Use for IP Protection,” 2007 CHES Cryptographic Hardware and Embedded Systems, Springer Berlin Heidelberg, p. 63–80. 10. D.E. Holcomb, W.P. Burleson, and K. Fu: “Power-Up SRAM State as and Identifying Fingerprint and Source of True Random Numbers,” IEEE Transactions on Computers, 2009, Vol. 58, No. 9, p. 1198-1210. 11. V. Leest, et al.: “Hardware Intrinsic Security from D Flip-flops,” Proceedings of theFifthACMWorkshoponScalableTrustedComputing, 2010, Association for Computing Machinery, New York, p. 53–62. 12. M. Cortez, et al.: “Modeling SRAM Start-up Behavior for Physical Unclonable Functions,” IEEE International Symposiumon Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012, Austin, TX, p. 1-6. 13. S.S. Kumar, et al.: “The Butterfly PUF Protecting IP on every FPGA,” IEEE InternationalWorkshoponHardware-OrientedSecurityandTrust, Anaheim, CA, 2008, p. 67-70. 14. S. Morozov, A. Maiti, and P. Schaumont: “An Analysis of Delay Based PUF Implementations on FPGA,” Proceedings of the 6th International Conference on Reconfigurable Computing: Architectures, Tools and Applications (ARC’10), 2010, Springer-Verlag, Berlin, Heidelberg, p. 382-387. 15. U. Rührmair and D.E. Holcomb: “PUFs at a Glance,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, p. 1-6. 16. U. Rührmair, H. Busch, S. Katzenbeisser: “Strong PUFs: Models, Constructions, and Security Proofs,” eds. A.R. Sadeghi and D. Naccache, Towards Hardware-Intrinsic Security, Information Security and Cryptography, 2010, Springer, Berlin, Heidelberg. 17. Xilinx, “XA Artix-7 FPGAs Data Sheet: Overview (DS197),” 2017. 18. Xilinx, “Xilinx Zynq-7000 SoC Data Sheet: Overview (DS190),” 2018. 19. R. Maes andV. Leest: “Countering the Effects of SiliconAging onSRAM PUFs,” IEEE International SymposiumonHardware-Oriented Security and Trust (HOST), 2014, p. 148–153. 20. JEDECSolid State Technology Association: “FailureMechanisms and Models for Semiconductor Devices,” JEP122E, p. 16-18. ABOUT THE AUTHORS John (Marty) Emmert received a bachelor of science degree in electrical engineering from the University of Kentucky, his master’s degree in electrical engineering from the Air Force Institute of Technology, and his Ph.D. in computer science and engineering from the University of Cincinnati. He is currently a professor with the Department of Electrical and Computer Engineering, University of Cincinnati, and the Director of the NSF Center for Hardware and Embedded Systems Security and Trust (CHEST) I/UCRC. He is also a graduate of the Air War College and a retired Colonel from the U.S. Air Force Reserves. AnveshPerumalla receivedhismaster’s degree inelectrical engineering from Wright State University and a Ph.D. in computer engineering from the University of Cincinnati. He is currently a post-doctoral researcher with the Department of Electrical and Computer Engineering, University of Cincinnati. His current research focus is on hardware security topics, such as physically unclonable functions, counterfeit IC detection, FPGA reverse engineering, and asynchronous circuit design methodologies.
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