edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Mary Anne Fleming Director, Journals, Magazines & Digital Media Joanne Miller Senior Editor Victoria Burt Managing Editor Allison Freeman Production Supervisor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Rosine Coq Germanicus Universitié de Caen Normandie Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Innovation Systems Rosalinda M. Ring Howard Hughes Research Labs LLC Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, jan@designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is published quarterly by ASM International®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright©2022by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $160 U.S. per year. Authorization tophotocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registeredwith theCopyright ClearanceCenter (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly toCCC, 222 RosewoodDrive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. With the involvement of numerous independent entities in themodernmicroelectronics supply chain, particularly considering the horizontal and globally distributed model, ensuring security and trustworthiness of modern system-on-chips (SOCs) has become a major challenge. At the same time, with the ever-increasing capacity and functionality of microelectronic devices, more security-critical information (secret keys, passwords, biometrics, and configuration bits) is stored in and processed by the SOCs, making themanattractive target for attackers. This issue is not unique toSOCs; the newheterogeneously integrated architectures built in 3D and 2.5Ddesign implementationwith advanced packaging technologies, such as systems-inpackage (SIP) architectures, also suffer from similar vulnerabilities. With the globalization of the design cycle and supply chain, attacks on microelectronic devices (SOCs or SIPs), have been on the rise. The academic community, industry, and government have discovered and reported numerous threats, including, but not limited to, malicious implants, counterfeiting, physical and side-channel attacks, information leakage, access control, fault injection, IP piracy, and reverse engineering. The potential sources of these threats and vulnerabilities span over different stages of the microelectronic supply chain, such as flaws in the design and integration, rogue employees (insider threat), untrusted third-parties, untrusted foundry, and malicious end users, to name a few. A number of methods have been developed to assess the design against these vulnerabilities at different stages of the design cycle during pre-silicon aswell as post-silicon stages. Example solutions include supply chain integrity (enabling end-to-endprovenance and traceability), IPprotectionandobfuscation (enabling secure key exchangewith provable security), runtimemonitoring (enablingmalicious behavior detectionduringmissionmode), and tamper detection (tampering detection including x-ray, optical, and laser). However, the emergence of the zero-trust model in the microelectronics supply chain in recent years as well as the ever-increasing complexity of microelectronic devices, the increasing trend in third-party IP reuse, and the involvement of distributed entities across the globe in the supply chain, have significantly escalated the challenges of establishing trust and assurance. Given the above-mentioned concerns, the followingmust be considered in securing future electronics supply chain: (1) Enabling EDA tools with security objectives for building security-by-construction using securitymetrics, properties, policies, enabling user-defined security assets’ definition, and automation for modeling and implementing security policies/properties at different NOVEMBER 2022 | VOLUME 24 | ISSUE 4 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL MICROELECTRONICS SUPPLY CHAIN SECURITY Mark Tehranipoor, University of Florida tehranipoor@ece.ufl.edu edfas.org Tehranipoor (continued on page 60)
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