edfas.org 1 7 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 cycles. In both Fig. 8a and b, ideal inter-chip and intrachip HD is shown using straight lines. It should be noted that all million challenge-response values are close to the ideal HD values. Merely increasing the number of challenge-response pairs by different permutations doesn’t necessarilymean thismethod leads to a strong PUF. To increase the strength of the PUF, the authors are currently researching and extending thismethod to use different LUT routing strategies. A six input LUT has 64memory cells and thismethod only uses two inputs out of those six to map the memory PUF. Thehypothesis is that different combinations of these input configuration should give different SUVs because of the underlying FPGA fabric routing changes. Key to this strategy is making sure the feedback path delays are balanced, otherwise it will result in an unbiased fingerprint. This strategy should not only exponentially increase the challenge-response pairs but also make it difficult for an adversary to predict the next pair. ARTIFICIAL AGING EXPERIMENT The aging experiment used five Xilinx Zedboards that have a Zynq 7000 processor with Artix-7 FPGA fabric. The processor’s operating temperature was between 0 to 85oC.[17,18] In order to artificially age the circuit boards, theywere placed in a temperature-controlled chamber at a desired temperature and voltage, using the age acceleration factor:[19,20] The parameters used for the test were based on a similar study:[19] gate voltage exponent, α = 3.5; time exponent, n = 0.25; activation energy, Eaa = -0.02 eV; Boltzmann’s constant, k = 8.62 x 10-5 eV/K; nominal voltage, Vnominal = 1.8V; nominal temperature, Tnominal = 23oC; higher stress voltage, Vstress = 2.5V; and higher stress temperature, Tstress = 80oC. After applying these parameters, we calculated an aging factor, AF = 163.99. This means one hour of accelerated aging gave 163.99 hours of estimated aging, which was approximately one week. Using AF = 163.99 in a temperature-controlled chamber for 255 hours resulted in approximately five years of artificial aging. For a more realistic analysis, these FPGA LUTs were programmed during the aging process. These circuit boards were taken out of the temperature-controlled chamber every 1, 2, 4, 8, 16, 32, 64, and 128 hours to measure the fingerprints at nominal conditions. For each aging cycle, we acquired (continued on page 20) Table 2 Average inter-chip and intra-chip HD of different 64-bit signatures permutated using a million challenge-response pairs on 10 FPGAs Million 64-bit challenge-response pairs Inter-chip HD (Ideal 50%) Average bits different Intra-chip HD (Ideal 0%) Average bits changing Average 48.9979 25.6571 1.0514 0.5505 Max 53 27.7527 2.6667 1.3964 Min 42.94 22.4873 0.0938 0.0491 Fig. 8 (a) AverageHDpercentage of amillion challenge-response pairs fromten FPGAs. (b) AverageHD values of amillion 64-bit challenge-response pairs from ten FPGAs. (a) (b)
RkJQdWJsaXNoZXIy MTMyMzg5NA==