edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 16 of incidence interference pattern is applied, and the response is compared against the known database of images. Using this technique, an optical PUF or reflective PUF creates a large database of (Ci RCi) pairs. The same concept is applied to the memometer PUF. The authors mapped 5180 memometer PUF cells on ten Xilinx FPGAs. On average, 97.08%of the bitswere stable. Figure 7 shows the probabilistic analysis of thesememory SUVs powering up to logic “1” for ten power cycles on an FPGA. It also shows the stable values in yellow and unstable values in dark blue. For this particular FPGA, out of 5180 SUVs, there are 5056 stable values (usable in fingerprints). These stable values are consistently logic “1” and logic “0” for each power cycle. Different permutations of LUTs are used to increase the number of (Ci RCi ) pairs. FPGAs give the flexibility to map different combinations of LUTs to form a single cross-coupled pair memory cell, and thus increase the total number of unique challenge-response pairs by an order of magnitude. To validate the hypothesis, a million different permutations of 5180 different SUVs in the LUT based memory values as (Ci RCi) pairs were programmed. Table 2 shows the average inter-chip and intra-chip HD of different 64-bit signatures taken using the million tested combinations of different challenge-responsepairs. An average of 48.99% inter-chip HD from themillion pairs was achieved. InTable 2, anaverage inter-chipHDvalue for each fingerprint is between 42.94% and 53%. An average of 25.65 bits out of 64 bits are different with an upper and lower boundof 27.75 and 22.48 bits respectively. Similarly, an average of 1.05% intra-chip HD was achieved. An average of 0.55 bits out of 64-bits are changing over time with an upper and lower bound of 1.39 and 0.049 bits. Figure 8a shows the average HD percentage and Fig. 8b shows the average HD values for themillion (Ci RCi) pairs simulated from ten different FPGAs for ten power Fig. 6 Inter-chip and intra-chip HD of a 64-bit memory signature on ten Xilinx FPGAs. Fig. 7 The probabilistic analysis of memometer PUF start-up values powering up to 1 on a Xilinx FPGA; stable values (yellow) and unstable values (dark blue).
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