edfas.org 15 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 shown in Fig. 4b. One of the challenges of this design is balancing feedback path delays. If the feedback routing paths are not matched, then thememory element produ- ces known values instead of random values. In previous works, “implementing a cross-couple element using combinational logic on an FPGA was not straight forward due to inability to create combinational loops;”[13] however, the authors have been successful implementing crosscoupled combinational elements using FPGA LUTs and balancing the feedbackpathdelays. Memory PUF research shows that 64 bits are enough to differentiate between all existing ICs (264 unique signatures).[10] To demonstrate the approach, the authors programmed 64 of these memometer PUF elements on ten Xilinx Artix-7 FPGAs. The same programming (*.bit) filewas used to programall ten FPGAs, and each FPGA gave a unique 64-bit memory signature. Figure 5 shows the probability analysis for fingerprint bits powering up to logic “1” values, where each row corresponds to a unique 64-bit fingerprint from a different FPGA. Figure 6 shows the probability distribution of the inter-chip and intra-chip HD of these 64-bit fingerprints for ten power cycles on all ten FPGAs. The x-axis represents the percentage of PUF output bits that are different from one FPGA to another for inter-chip HD, and PUF output bits that are changing over time for the intra-chip HD. An average inter-chip HD of 49.7% (vs. an ideal HD of 50%) and intra-chip HD of 0.88% (vs. an ideal HD of 0%) was achieved. These values demonstrate fingerprint uniqueness and reproducibility. JOURNEY TOWARD A STRONGER PUF PUFs are generally categorized as weak or strong.[7] A weak PUF contains a limited number of challengeresponse (Ci RCi)pairs,whereasastrongPUFcontainsa large number.[15] Both SRAM and butterfly PUFs are categorized as intrinsicweakPUFs[15] due to their fixednumber of (C iRCi) pairs—most cases typically have one challenge at powerup. Weak PUFs are mainly used in cryptographic systems where a secret key is derived from the PUF response with the help of error-correction codes. On the other hand, a strong PUF not only contains many (Ci RCi) pairs, but also makes it difficult for an adversary to predict the next response.[16] The approach of creating a large number of (Ci RCi) pairs is similar to a reflective PUF or optical PUF. [7] For example, reflective PUFs are used in identifying missiles: a light scattering particle is sprayed onto themissile and an inspector records the images of this particle by illuminating it at different angles. Each angle of incidence gives a unique response, which is recorded and stored in a secure database. For authentication, a random angle Table 1 Butterfly PUF compared to memometer PUF Butterfly PUF Memometer PUF Uses cross-coupled latches Uses cross-coupled LUTs Complex implementation and routing Simple implementation and routing Difficult to balance feedback path delays Easy to balance feedback path delays Requires three sets of paths to be symmetric for ideal SUVs Path 1: Global clock to clock pin (clock skew) Path 2: Excite signal to CLR/PRE Path 3: Feedback path delay (latch 1 output Q -> latch 2 input D) Requires only one path to be balanced Feedback path delay (LUT 1 output F -> LUT 2 input A) Requires external signal to settle into an unstable state for startup behavior Does not require any external signals for start-up behavior One challenge-response pair Hundreds of challenge-response pairs Fig. 5 The probability analysis of a 64-bit memory signature powering up to 1 on ten FPGAs.
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