edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 4 14 MEMORY PUFS Memory components (such as SRAMs and D-FFs) are essential elements in electronic systems. Memory based PUFs use these basic elements to create fingerprints. When a cross-coupledmemory structure ismanufactured for minimum size, as shown in Fig. 3, the relative drive strength and doping levels are usually balanced. When these devices are powered on, before programming any value, the metastability property of balanced memory elements leads to random start-up values.[9-11] Instability within these cross-coupled components is due to several technological and non-technological parameters, such as probabilistic geometry of transistors, inexact threshold voltages, or channel length modulation.[12] Because of these varying parametric values, some memory cells always power on to a specific state, whether logic “1” or logic “0;” that is, 100%of the time these cells are powered on to the same logic value. However, other cells fluctuate between logic “0” or logic “1” for each power cycle. A fingerprint is created by estimating themost likely power-up state of each memory cell SUV.[10] MEMORY PUFS FOR CONTEMPORARY FPGAS One major disadvantage of applying memory PUFs to contemporary FPGAs is that many newer FPGA families come withmemory preset. In other words, as soon as the FPGA is powered on, the memory elements within in the FPGA are preset to either logic “1” or logic “0” by default. This makes memory PUFs impractical. One notable effort to overcome this particular problem was the invention of the butterfly PUF (BPUF).[13] The BPUF emulates SRAM behavior at power-up. The BPUF uses built-in FFs configured as cross-coupled latches to emulate memory PUFs, as shown in Fig. 4a. The preset (PRE) signal sets the output of a latch high, and the clear (CLR) signal sets the output low. The BPUF operation starts when the excite signal— connected to the PRE of one latch and CLR of another latch—is set to high for a few clock cycles and brought to low. The BPUF will settle to either logic “0” or logic “1” at the output. The output SUVs are based on the intrinsic characteristics of the FPGA. A key challenge with this implementation is that the quality of SUVs will purely depend on the symmetric construction of the BPUF cell. As shown in Fig. 4a, the red and green routing paths must be routed identically. In other words, the delay difference between the signals should be equal down to picoseconds. Unlike ASICs, FPGA routing paths arenot easilyaccessible to thedesigner. Even though FFs are readily available on almost all FPGAs, the symmet- ric construction of a BPUF makes it challenging to imple- ment for different FPGA architectures. A similar research study concluded that a BPUF is not an ideal candidate for anFPGA.[14] This has led to the inventionof thememometer PUF,which is amuchsimpler implementationof emulating SRAMstart-upbehaviorusingLUTs.Table1shows themajor differences between the BPUF and the memometer PUF. MEMOMETER The memometer PUF is implemented by mapping cross-coupled NAND gates to cross-coupled LUTs, as Fig. 3 Common cross-coupled memory structures: SRAM and D-FF. Fig. 4 PUFs for contemporary FPGAs that imitate SRAM PUF. (a) (b)
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