August_EDFA_Digital

edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 3 42 TECHNICAL SESSIONS Symposium sessions will be packed with high quality, innovative, and original unpublished pre- sentations on several topics: • Emerging FA Techniques • System-in-Package and 3D Devices • AI Applications for Failure Analysis • Die Level Fault Isolation • Package Level Fault Isolation • Nanoprobing and Electrical Characterization • Scanning Probe Analysis • Sample Preparation and Device Deprocessing • FIB Sample Preparation • FIB Circuit Analysis and Edit • Microscopy and Materials Characterization • Packaging and Assembly • Board and System Level Failure Analysis • Case Studies: Device Analysis • Case Studies: FA Process • Hardware Attacks, Security, and Reverse Engineering • Detecting and Preventing Counterfeit Microelectronics • Product Yield, Test, and Diagnosis in electrical engineering fromStanfordUniversity, Crabbé joined the IBMResearch Divisionwhere he participated in the early SiGe Heterojunction Bipolar transistor program. He was the first to demonstrate bipolar transistor opera- tion above 100 GHz in a silicon-based technology. Crabbé then joined theMicroelectronics Divisionwhere he led the transistor design anddevelopment for several generations of CMOS technologies. More recently, he has beenworking closely with processor designers to optimize technology features in order to deliver leadership processor perfor- mance for IBM Systems. His talk is called “CMOS Scaling: Where ToNext?” andwill review the semiconductor indus- try progression from planar to FinFETs to NanoSheets with their respective benefits and implications for failure analysis. Read more about Crabbé’s keynote topic on page 2 in this issue. The panel discussion is a unique and vital event in every year’s ISTFA conference. It is designed to have dynamic and interactive discussions with both panelists andaudiences fullyengaged. This year’sdiscussion follows the conference theme of FA challenges and solutions of smaller and hard-to-find defects. A group of distinguished experts/panelists fromdiverse fields will share their expe- riences on this subject. Come with your questions, chal- lenges, suggestions, tips, and tricks for this exciting event. As semiconductor technology evolves, FA techniques and methodologies also need to evolve to keep pace. In response to this, anFATechnology Roadmapwas initiated. In recent years, targeted gap analyses were conducted at the ISTFA session level to identify current technical challenges and potential solutions. Last year, a new FA Roadmap framework was established to form three tech- nical councils. Die-level (with Isolation and Post-isolation domains), Package Innovation, and FA Future councils were constructed to better define and extend our level of understandingof technical challenges. This year, ISTFAwill dedicate a 1.5-hour session for the FA Roadmap council chairs to share summary reports of their findings. This is a great opportunity for attendees to understand the current challenges facing our industry and for vendors to reconcile their own roadmaps with such findings while collaborating with the appropriate councils to identify potential solutions. The Expo is always a popular event at ISTFA conferenc- es. So far, more than 50 vendors have signed up and they will showcase the latest tools, techniques, and solutions in the FA field, such as test, diagnosis, fault isolation, sample preparation, imaging, and characterization. The Expo brings tool and technique suppliers and users together to the benefit of both parties. Vendors get feedback from users for further improvement, while users can visit differ- ent vendors at one time and compare solutions to select one suitable for their work. The two-day Expo takes place on Tuesday and Wednesday. A Tools of the Trade Tour on Lush Pasadena cityscape.