August_EDFA_Digital

edfas.org 35 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 3 engineering of packages and PCBs. Construction analysis may be done to verify an electronic device for possible patent infringement or for competitive analysis. With the advent of hardware Trojan threats, there is a growing interest to examine PCBs and packages to verify if their electrical components and traces conform to original designs. Reverse engineering is also used extensively by OEMs to fabricate their own versionof boards so as tohave similar functionality but be structurally slightly different from the existing manufacturers. It is also being used to duplicate parts and components of obsolete legacy equipment, vehicles, ships, or airplanes still used inmany governments and the military, where the original design files no longer exist. To show how this tool may provide a critical solution, wewill illustrate themontage or stitching Fig. 6 Comparison of the same region imaged in 6 min (top) vs. 87 min (bottom). Feature clarity is preserved at the shorter exposure time, suitable for fast cold joint/partial wet detection. Voxel size is 0.5 µm. Fig. 7 Comparison of the novel 3D x-ray system against a conventional XRMshowing the suppression of beamhardening artifactswith the former (image on the right). together of several high-resolution scans cover- ing the entire surface area of an intact PCB. In failure analysis or reverse engineering applications, another exciting benefit of this tool is the elimination of beam hardening artifacts (streaks, bands, and noise) typically encountered in tomography of semiconductor packages. This artifact is causedwhenmetals embeddedwithin organicmaterials in the path of x-rays are attenu- ated at different rates, especially as the package or PCB is being rotated. These streaks or bands may mask defects or make the segmentation of circuits or structures in reverse engineering very difficult. RAPID STRESS TEST EVALUATION AT 0.7 µm RESOLUTION IN 30 MINUTES Burn-in test is a method for detecting early failures in semiconductor devices also called “infant mortality.” It requires the testing of devices under a set of stress conditions that usually involves an elevated temperature of 125 to 150°C though some “high-reliability” device may be tested at 200°C or higher for a set number of hours. During this time the devices are biased with power applied to them. The ability to rapidly evaluate the effect of time or biasing conditions on the whole batch of these devices is illustrated in Fig. 4. CRACK AT RDL INTERFACE AT 0.3 µm VOXEL Redistribution layers are the copper metal intercon- nect sheets that electrically connect one part of the semiconductor package to another. They redistribute the I/O access to different parts of the chip and make it easier to add microbumps to a die. Redistribution layers are typically used in fan-out and 2.5D/3D packages. Because the Cu sheet is very thin, it is usually challenging