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edfas.org 25 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 3 electrical modes. In particular, the impact of the applied voltage during measurements is examined. DTI STRUCTURE AND EXPERIMENTS Silicon high aspect-ratio DTI structures designed for inter-device and substrate isolation are studied. DTIs are patterned in a complementary BiCMOS silicon substrate used for microwave to millimeter-wave applications. A (100) oriented, p-type silicon substrate (Si p-substrate) with a resistivity of 200 Ωcm is used. At the beginning of the process, the DTIs are etched into the silicon substrate by deep reactive ion etching (DRIE). The trenches are filled with a deposited oxide liner and low-pressure chemi- cal vapor deposition (LPCVD) polycrystalline silicon. To avoid local current along the DTI structure, a channel stopper made with a boron (p+) implantation is formed at the bottom of the trenches followed by an annealing. By using chemical-mechanical planarization (CMP), the wafer is planarized. The front-end process continues to formpassive and active (bipolar and BiCMOS-RF) devices. Metal depositions end the processmodule for self-aligned devices. Figure 1 presents a schematic cross-sectional view of the DTI structures. The DTIs delimit the locations for the co-design of four devices on the same silicon chip. To analyze the sample structure, SCMand SSRMbased on an AFM are deployed. SCM allows mapping majority carrier levels and their types (n- or p-) in semiconductors. A conductive AFM tip scans an oxidized surface in contact mode. The AFM tip acts therefore as themetal electrode in ananometricmetal-oxide-semiconductor (MOS) structure. An alternating voltage (V AC ) is applied to modulate the free carrier movement in the semiconductor under the contact to generate a local capacitance variation formed by the conductive tip and the sample. A DC bias voltage (V DC ) can be applied. The local variation dC/dV at each pixel is then measured in terms of phase and amplitude. Fig. 1 DTI structure for inter-devices and substrate isolations. The DTI structures are etched in a silicon p-substrate, decorated with a channel stopper, and filled with oxide and polysilicon. For device 3, between the DTI structures, a buried p-type (BP) layer is integrated. Fig. 2 (a) SCM technique based on an AFM for doping detection, and (b) simulated dC/dV curves for the equivalent nano-MOS contact for several doping levels. (a) (b)