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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 3 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Allison Freeman Production Supervisor Joanne Miller Managing Editor Victoria Burt Contributing Editor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh Qualcomm Ted Kolasa Northrop Grumman Innovation Systems Rosalinda M. Ring Howard Hughes Research Labs LLC Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright©2022by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $160 U.S. per year. Authorization tophotocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registeredwith theCopyright ClearanceCenter (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly toCCC, 222 RosewoodDrive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. T he semiconductor industry has made extraordi- nary progress in the past few decades with lateral scaling now superseded by new transistor archi- tectures exploiting the third dimension. Fin field-effect transistors (FinFETs)were introduced in production in 2011 at the 22 nm node and are now ubiquitous in all leading- edge logic technology nodes. They replaced planar transistorswith improved scalability, superior drive current per unit area, and better electrostatic control, and they are expected to remain in production until 4 nm or 3 nm technology nodes are available. The next step toward an ideal device structure for best I on -I off control is the gate-all-around transistor architecture, andmultiple geometric variants have beenunder exploration for over 15 years. They evolved froma single nanowire to stacked nanosheets for technology competitiveness over FinFETs. Stacked nanosheet transistors, first demonstrated by IBM in June 2017, stand out by their superior drive current per unit area, stacking typically three nanosheets on topof eachother. Introduction inproduction is targetedat 3nmandbeyond with wide industry adoption for leading-edge logic technologies and under various names such as multi-bridge channel FET, and nanoribbon. Beyond nanosheets, the vertical-transport nanosheet device and tran- sistor stacking are promising new architectures under development, which overcome scaling limitations. All these device architectures provide new challenges for failure analysis as they approach atomic-scale dimensions. AUGUST 2022 | VOLUME 24 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL CMOS SCALING: WHERE TO NEXT? Emmanuel Crabbé, IBM crabbe@us.ibm.com edfas.org Crabbé Emmanuel Crabbé’s keynote will be held Tuesday, November 1, 8:30-9:30 a.m. PT. For more information about the conference, see the ISTFA preview on page 41 and visit the website at istfaevent.org.