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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 36 tools, e.g., clock tree properties and utilization factors. The objective is to achieve a Pareto optimal design with as few runs of the P&R tools as possible. Researchers at NC State, led by Professors Rhett Davis and Paul Franzon, applied machine learning to this problem. Their goal was to predict the optimal design point—or the Pareto front—and the corresponding P&R parameters. An initial model is developed using 50 to 150 runs of the P&R tool for an existing design. Transfer learning is then used to create a useful model for a new, i.e., previously unseen, design in as few as 10 runs and with better than 96%accuracy. Sample results are shown in Fig. 1. In the second project, a team led by Prof. Sung Kyu Lim of Georgia Tech used ML to predict the achievable PPA for a given netlist, without performing physical design. First, the physical design process was broken into placement, routing, timing closure, and engineering change order (ECO) steps, and then each step was addressed in turn. Here, we summarize the work related to the clock routing step. A generative adversarial network (GAN) approach is used to train an ML model that learns from an existing clock routing database and predicts clock power and skew for new designs (see Fig. 2). Subsequently, from a placed netlist, it is possible to predict post-clock routing PPA without having completed the routing. CAEML’S FUTURE CAEML recently applied to the NSF for a Phase 2 IUCRC grant and the center is actively recruiting new members to the prospective Phase 2 center. In an IUCRC, industry membership fees are pooled to support the research and the sponsored research projects are selected collec- tively by the center’s industry members. Inquiries about membership may be directed to the center’s Operations Manager or to the Site Directors, whose contact informa- tion may be found on the center’s webpage, go.illinois. edu/caeml. REFERENCES 1. P. Kashyap, et al.: “2Deep: Enhancing Side-channel Attacks on Lattice-based Key-Exchange via 2-D Deep Learning,” IEEE Trans. on CAD, 40 (6), 2020. 2. L. Francisco, et al.: “Fast and Accurate PPA Modeling with Transfer Learning,” Proc. IEEE/ACM MLCAD Workshop, 2021. 3. Y.-C. Lu, et al.: “GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019. Fig. 2 A GAN is used to create synthetic clock trees as part of the PPA predictor. [3]