May_EDFA_Digital

edfas.org 31 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 of nanometers. [1] Sputtering or deposition and oxidation thickness are also in the nanometer range. During fabri- cation, if the adversaries intentionally change the recipe of these process parameters, it will change the original thickness, which is difficult to notice during inspections. Hence, the threat level for oxidation and deposition is higher compared toother fabricationprocesses. This could result in reliability problems like insulation breakdown, cracking of RDLs, early breakdown, andTSV deformations. The next step is filling/injecting Cu in the trench and formingaTSVusing theCu fillingmethod. Acareful process is followed to fill the trench so as to eliminate any void formation. At this point, an adversary may intentionally try to change the parameters and form a void that may lead to issues like increased latency and device failure in the later application stage. The reliability threat is mod- erate during the etching and Cu filling step because any malicious activity will develop voids in the TSV, which can be detected using x-ray imaging [8] with moderate efforts. After filling the copper, a CMP process is followed to polish or remove the excess copper if present on the substrate. Changing the parameters may lead to warpage and crack in the substrate that would be easily detected during the process. The reliability threat for underfilling and CMP is comparatively low, as the vulnerabilities in these steps could be easily detected in the subsequent fabrica- tion stages. EXISTING COUNTERMEASURES AND SOLUTIONS The current assurance techniques in the packaging industries are not focused on security assurance; instead, they are tested for defects, durability, reliability, and failure analysis for specific predefined conditions. The engineers design the process for fabrication, and the designated techniciansmonitor theequipmentworkflow. The security assurance of the package has highly relied on the equip- ment process flow and the technicians. If any adversaries try to change specific fabrication process parameters, it is unlikely to be tracked unless and until anyone reports it. Moreover, defects are prevalent in the packages; there- fore, it is implausible that anyone could detect this as a reliability and security threat. After fabrication, physical inspection is a prevalent assurance technique for package assurance to identify defects, testing for electrical connection, temperature, and vibrational shock resistance. For inspection and failure analysis, both nondestructive and destructive identification techniques are used. [9] Based on chip com- plexity and material composition, the efficacy of various detection methods varies greatly, so several strategies in the verification process must be leveraged. However, the existingphysical inspections are performed in the industry after fabrication, assuming any adversaries have notmali- ciously compromised the chip. These techniques do not completely assure that the packaged chip is not compro- mised and would not intentionally fail by the adversary’s actions during the fabrication. There is no significant inspection method applied in the package to verify the specified design during the fabrication process. Instead, a predefined electrical connection is tested. However, a nondestructive technique fails to provide complete assurance if any malicious design is implemented in the package. Although nondestructivemethods of inspection donot provide robust assurance of complicatedpackaging components, these needs can be fulfilled by destructive methods such asmolding compound characterization and internal inspection. [9] However, these techniques can only partially resolve the concerns mentioned above; more rigorous detection techniques are needed for full internal packaging characterization. PROPOSED COUNTERMEASURES Physical inspection and assurance techniques could be followed to detect and avoid potential security threats during andafter fabrication. The threemajor players: engi- neers, equipment, and technicians, could be monitored regularly. The key fabricationparameters like photolithog- raphy, oxidation, and deposition process could be tracked down during the fabrication process using advanced automated artificial intelligence (AI) techniques. Based on the threat ranking, the process should be classified and identified for inspection priorities. For instance, TSVwalls fabricatedwithmore than or equal to 90°may result in im- perfect connection and potential reliability issues. Hence if this parameter is monitored during fabrication, it will avoid any catastrophic reliability threats related to TSVs. A nondestructive approach for physical inspection can be used to inspect the inter-structure and material of ICs, which is very important for interposer verification. However,most of thephysical inspections lack the capabil- ity todetect the structure andmaterial simultaneously. For instance, an x-ray image has limitedmaterial information. Therefore it is mainly useful for real-time verification in structure characterization such as scratches, broken links, and related faults rather than full assurance. They lack the capacity to provide robust total assurance. Fourier- transform infrared spectroscopy (FTIR) is used for packing material characterization, which is time-consuming and does not carry enough structure information.