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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 30 on current and upcoming supply chain fabrication threats and potential countermeasures. The following section includes a detailed assessment of potential vulnerabili- ties in the interposer because of the malicious changes in fabrication parameters. VULNERABILITIES OF INTERPOSER FABRICATION Different threat models in fabrication are divided into two significant threats, security threats and reliability threats, marked in red and yellow, respectively, in Fig. 6. Such threats are mainly developed by an untrusted foundry or rogue employees in a trusted foundry. For instance, masking and patterning in photolithography are crucial for a trusted IC packaging, irrespective of the trusted and untrusted foundry. This step, however, is vulnerable to a data breach if the original mask design is replacedwith amalicious design by an untrusted foundry or a rogue employee in a trusted foundry. It will replicate the malicious pattern on the wafer during fabrication, which might be later used as a backdoor for stealing assets or adding trojans. This malicious change in the lithography mask may not be noticed at any stage of the fabrication. Although a certain level of knowledge and skill set is required to carry an attack in the photolithography process, less expert and trained attackers can also cause a malicious change in the rest of the process. Minor tweaks and changes in the set-up parameters during the fabrication, asmentioned above, will cause an intentional failure after prolonged usage or under certain circumstances. This electrical component failure might result in catastrophic system failure while it is being used in critical applications. For example, in the case of etching, the process involves DRIE, which is responsible for creat- ing a big trench in the wafer for TSVs. If the parameters of performing DRIE are maliciously changed, the TSV fabri- cated will become unreliable, creating a reliability type threat related to TSVs. While forming a trench, an angle of less than 90° is important for void-free TSV, which can be compromisedby changing theDRIEparameters. The other step in etching is non-Bosch and isotropic etch, which are used for smoothing the rough trench created by the DRIE process. [1] If the parameters for etching are changed maliciously, the quality of TSV will be compromised and may cause intentional reliability issues likemalfunctioning and circuit breakage. After etching, the next step is the oxidation of SiO 2 , which needs a high temperature at the range of 1050°C. The time for oxidation is from30mins to a couple of hours, depending on the thickness needed. Oxidation provides isolation between the copper filled in the TSV trench and the silicon substrate. [1] By changing the important oxida- tion parameters like time and temperature, the thickness of the oxides can be controlled, andmaliciously changing the thickness may lead to reliability issues in the inter- poser. The impact of changing the oxidation thick- nessmaliciouslywill cause issues like short circuits, leakage of current during long time application, and the whole systemmay fail during critical operation. Since the oxidation thickness is pre-calculated and based on that, the temperature and time are set on the equipment for thermal oxidation. However, there is no in-process verification to measure the oxidation thickness after thermal oxidation. If amali- cious attacker changes the parameters of a specific batch of wafers during the oxidation process, the oxide thickness will be changed and go unnoticed. Hence, it would be the reason for the catastrophic failure of devices in critical functionality. Following oxidation, the next step in interposer fabrication is deposition, where a thin layer of Ti and Cu is deposited using sputtering or thermal evapo- ration. The importance of Ti and Cu is to provide a good contact bonding between the silicon substrate and the copper that will be filled/injected in the TSV trench. This process is also called seed layering. The range of seed layering thickness is of the order Fig. 6 Threat model for interposer wafer fabrication.