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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 28 PHYSICAL SECURITY ROADMAP FOR HETEROGENEOUS INTEGRATION TECHNOLOGY (continued from page 25) electrical barriers for the Si-substrate and metal layers. The normal temperature for oxidation is 1050°C. Before filling the TSV’s trenchwith copper, a seed layer of titanium and copper is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). After seed layer deposition, the remaining trench is filled with Cu deposition. During the Cu filling, excessive copper is deposited on the interposer substrate. To remove this overburden of copper, CMP is usednext for backsidewafer polishing. CMP has evolved as a vital step in integrated circuit fabrication for achieving global surface planarization of diverse thin films in front- and back-end processes. INTERPOSER OVERVIEW Interposer technology enables 2.5D and 3D stacking, which can incorporate side-by-side and vertical alignment of the chips in a single package. The interposer offers inter- die communicationandaccommodates a specific underly- ing interconnect fabric at the device level that resembles a contemporary printed circuit board version. Many pro- ducts are currently available with interposer technology, notably the AMD Fijy/Fury GPU and the Xilinx Virtex-7 FPGA. Xilinx has launched four products in its Virtex FPGA family that use TSMC’s chip on wafer on substrate (CoWoS) technologywith silicon interposers. Intel recently developed a 3D packaging technology called Foveros to combine high-performance CPU, GPU, and AI processors. Interposer-based integration has also been considered by other companies suchas Cisco, Altera, andMicron, andhas roadmaps that display potential implementations of an interposer. The implementations of interposers are both passive and active in design. INTERPOSER VS. PCB The outsourced semiconductor assembly and test (OSAT) firms and foundries have put a great deal of work into designing advanced packaging of the system in package (SIP) to back up Moore’s law, including but not limited to fan-in, fan-out wafer-level packaging (WLP) panel-level packaging, (PLP), 2.5D and 3D pack- aging. Advanced IC packaging requires a large amount of design and process specifics, which increases the efficiency of the final die. Like PCBs, interpos- ers are also used to mount several chips later- ally stacked side-by-side in the nearest possible proximity in a single package as shown in Fig. 3. The interposer forms a foundation for mounting the chips even with different node technologies and provides contact between the interposed dies with a high density and high bandwidth direction. FPGA, memory units, MEMS sensors, transceiver modules, power control blocks, cryptomodules, etc. can also be accommodated. The security evaluation of such advanced packaging, though, has been left behind. This segment addresses the relation between PCBs and interposer-based advanced packaging technology from the hardware tampering per- spective and the “Big Hack attack” published by Bloomberg news. [6] The confidentiality of the motherboards of Super Micro Computer Inc. (Supermicro) has been violated, according to the report. Themotherboards of the PCBwere found to have a small malicious chip as represented in Fig. 4, such that every time the server booted up, it infected the motherboards with malware. It is alleged that the adversaries embedded themali- cious chips onSupermicro’smotherboards. [7] The consequences for this type of attack claimed to Fig. 3 PCB vs interposer comparison, a typical PCB mounted with components (left), chips closely packaged mounted on interposer (right). Fig. 4 Potential Trojan insertion in the interposer for DoS type attack intent.