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edfas.org 25 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 (continued on page 28) details of the interposer wafer is given; different attack models, security threats, and reliability challenges on the interposer level are explored. An overview of vulner- abilities and the requirements for the assured inspection process in fabrication is provided. The rest of the article is structured as follows: The second section provides an overview to explain interposer for advanced packaging technologies, interposer fabricating parameters, printed circuit board (PCB) vs interposer relationships, and appli- cations. The third section addresses all the potential vul- nerabilities of the fabrication process andmaterial-based security and reliability threats. Finally, potential counter- measures will be introduced and discussed to detect and provide assurance against the threats addressed. BACKGROUND In the early days of semiconductor packaging, flat ceramic packs were the most dominant method used for many years due to their stability and compact scale. Commercial circuit packaging soon shifted to the dual in-line package (DIP), first in ceramic and then plastic. The realistic limit for DIP packagingwas surpassed by VLSI pin counts in the 1980s, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages. However, industries moved from PGA packages to land grid array (LGA) pack- ages in the 2000s. Since the 1970s, ball grid array (BGA) packages have existedbut developed in the 1990s into flip- chip ball grid array (FCBGA) packages. [4] FCBGA packages allow the pin count to be much higher than any current form of package. The die is placed upside-down (flipped) in an FCBGA package and attaches to the package balls via a substrate identical to a PCB instead of wires. Figure 2 shows typical packaging techniques for ICs. Recent interposer innovations include the mounting of several dies in a single package called SIP or a three- dimensional integrated circuit for a device in the package. Silicon interposer is a technologywithmore than 20 years of experience in various versions. [5] Interposer-based tech- nology has generated a remarkable response in advanced packaging, where packaging foundries have become one of the key players in the semiconductor industry. The interposer provides a foundation for mounting the chips and contact between the interposed dies with a high density and high bandwidth direction. [3] For example, in a single die systemon chip (SOC), packing amemory chip and a logic chip together eliminates the delay of memory- processor communication and may also act as cache memory. A similar benefit is when a chip is fabricated in different technology nodes but packaged in a single inte- grated circuit using interposer-based advance packaging techniques. This packaging method also makes it easier to incorporate an analog ormixed-signal chip into a digital chip, with numerous applications in 5G or radiofrequency networking fields. The interposer has a high-density I/O pin interface, a low thermal expansion coefficient (CTE), and a high thermal transport coefficient to offer more stable packaging for heterogeneous integration. The fabrication of interposers includes two main stages, front-side and backside processing with multiple steps of photolithography, etching, oxidation, deposition, and CMP. [1] Front-side processing involves the fabrication of TSVs, RDL, and UBM, whereas the backside process involves the fabrication of RDLs and UBM. A high-level overview for each step and discussion on how an adver- sary may introduce vulnerabilities at each stage is given. The first and most crucial step in fabrication is photo- lithography, which involves the process of spin coating, masking, patterning, baking, and developing. In this step, the substrate is spin-coated with a photoresist, and the pattern is developed after the UV exposure. Photo- lithography is the most vulnerable stage in fabrication which may cause IP piracy or data leakage threat if manipulated by adversaries. Tampering other steps in the fabrication process mainly result in reliability or DoS- type threats. The etching includes three main steps: Bosch etch or deep reactive ion etching (DRIE), non-Bosch etch, and isotropic etch. In this step, deep trenching in the range of micrometers is performed for the copper filling in TSV formation. The oxidation process is used to forma layer of silicon dioxide (SiO 2 ) on the wafer. SiO 2 layer is used to provide Fig. 2 Packaging representations for (a) 2D, (b) interposer or 2.5D packaged chips with high bandwidth memory(HBM) and (c) 3D packaging methods on the interposer. (a) (c) (b)