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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 24 PHYSICAL SECURITY ROADMAP FOR HETEROGENEOUS INTEGRATION TECHNOLOGY Aslam A. Khan, Chengji Xi, and Navid Asadizanjani Florida Institute for Cybersecurity Research, University of Florida, Gainesville, Florida khanaslam@ufl.edu EDFAAO (2022) 2:24-32 1537-0755/$19.00 ©ASM International ® INTRODUCTION An interposer with fine pitch through-silicon vias (TSV) has become an attractive solution for homogeneous and heterogeneous high-density connection of multi-chips to form a system in package (SIP). [1] Because of its simple design and the micrometer technology scale, the inter- poser fabricationusually does not require high-end equip- ment and skillsets as compared to transistors and other advanced node technologies. Its fabrication includesmul- tiple steps, includingphotolithography, etching, oxidation, deposition, and chemical mechanical polishing (CMP). [2] It is a critical part of integrated circuits (ICs) for high-density I/O interconnection andbandwidthpackaging solutions, [3] which means all the data including sensitive information bits might pass through them. Theelectronics supply chain’s challenges andcomplex- ity make the interposer vulnerable to various attacks by adversaries that may cause confidential data leakage by adding malicious design elements during the fabrication process. The attackers may try a malicious attempt to cause a denial of service (DoS) type defect by intentionally changing the interposer design and fabrication param- eters. These changes will make the interposer vulner- able to failure while using it in critical applications. The attackers can be classified as an untrusted foundry or a rogue employee froma trusted foundry. With technologi- cal advancement, semiconductor fabrication has spread worldwide for business reasons such as cost and availabil- ity. As the fabrication process is now mostly outsourced offshore, it has opened the gate for new vulnerabilities. The following sectionwill discuss the threemain elements of the interposer named as through-silicon via (TSV), redistribution layer (RDL), and under bump metallization (UBM), shown in Fig. 1, where the malicious changes may be done in interposer fabrication. Through-silicon via is the largest part of an interposer and is used for providing connections from the front to the backside of the package. It is a critical component that provides interconnection for the interposer. It is fragile, and any malicious changes like adding an extra trench in the design, intentionally changing the dimensions, and introducing voidsmay cause security or reliability threats. Redistribution layer is the supporting component responsible for traversing and connecting TSVs in the front side aswell as the backside of an interposer. Delamination and cracks between theRDL andTSVs interface, if leftunin- tentionally or placed maliciously, can risk the reliability and security of the chip through the interposer. Under bump metallization is the last process in inter- poser fabrication and is responsible for creating micro bumps and controlled collapse chip connection (C4) to establish an external connection to the interposer. The intermetallic compound (IMC) layer formingbetweenUBM and bumps can potentially cause connection problems and security issues if implemented maliciously. Currently, there are no rigid approaches available to assure the fabrication process. The low technology requirement and offshore fabrication are the two main reasons which give rise to the security problems of the interposer. In this article, an overview of the fabrication Fig. 1 Some key elements of an interposer structure in advanced packaging for 2.5D, 3D, and heterogenous integration.