May_EDFA_Digital

edfas.org 21 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 2 of the sample surface. The estimated rate of material removal was determined to be 4 nm per minute for the acceleration and gun voltages of 100 eV and 500 eV respec- tively at 10 degrees. This process has a better control for layer-by-layermaterial removal compared to conventional mechanical polishing. The use of TEMsample preparation for SCMapplications presentsmany challenges. As stated previously, some of the critical issues needed to address include: 1) waterfall or curtaining elimination, 2) amor- phous layer removal, and 3) providing an adequate electri- cal contact to the sample through the TEMgrid. The initial preparation of an inverted prep TEMsamplewas done in a FIB-SEM, using a gallium-ion beam. Fiducial marks using oxide and platinum FIB depositions are placed targeting the specific device of interest. The process then begins with normal TEM inverted-preparationmethodswhere an in-situ liftout is performed. The sample is then flipped 180 degrees, such that the gallium-ion beam now mills from the underside of the device. This method minimizes the “curtaining” effect due to differential milling rates of the various device materials in the region of interest. Then thinning is performed on only one face of the sample. Milling begins at 30 keV for the rough mills, eventually dropping down to 5 keV as the target end point is reached, thereby leaving approximately 10-15 nm of amorphous material on the face of the sample. The amorphousmate- rial will subsequently be removed by the non-gallium- based FIB or a combination of ionmilling tools which will be discussed in detail in following sections. Figure4 shows optical, SEM, andTEM images of a14nm SRAM array in a cross section. Figure 4a shows a small silicon chip fragment attached to the side of the rectangle bar on a TEM grid. The sample is positioned in such a way to minimize stray capacitance between the SCM cantile- ver and the grid. As shown in Fig. 4b, the sample surface toward the silicon side is smooth and the waterfall effect is away from the front end of line (i.e., toward the back end of the line). Figures 4c and d show the Pt wire for electrical connection and TEM image of the SRAM array, respectively. RESULT AND DISCUSSIONS Figure 5 shows SCM dopant, or carrier density profile for location-specific, 14 nm FinFET devices prepared by mechanical polishing and FIB-based reference marking. A silicided-silicon [14] probe was used to take advantage of its superior sharpness, durability, and high resolution. Both N4 and P4 signals were captured as shown in layout of Fig. 2. All of the carrier profiles looked normal except on the rightmost fin of P4 (denoted by awhite arrow in Fig. 5). Although a carrier-related defect was found on the failing device, it was unclear whether it was an area of high or lowdopant concentrationwith respect to the surrounding area. SCSwas performed in the region of interest to better understand the dopant/carrier concentration at the defect location. A series of SCM images were taken at different DC bias conditions (0 V, ±0.5 V, ±1.0 V, ±1.5 V, ±2.0 V) while keeping the ACbias at a constant amplitude and frequency (0.5 V at 60 kHz). Electrical biaswas applied via the sample stage. SCS showed that the defect site was more n -type than the area around it and provided a source-to-drain leakage path. Figure 6a shows the layout of PFETs (P0, P1) andNFETs (N0, N1) of the SRAMarray in 14 nmFinFET technology pre- pared by the inverted TEM sample-preparation method. The NFETs (N0, N1) are double-fin devices whereas the PFETs (P0, P1) are single-findevices as shown in the layout. Thehigh-resolution topography image inFig. 6b shows the spatially resolved fins which correspond to the layout in Fig. 6a. For illustration purposes, all the devices (N0, P0, N1, P1) have been shown. The topography image clearly shows the areas of the double-fin (N0, N1) and single-fin devices (P0, P1) with surface roughness of less than 5 Å, which is critical for dopant profiling. To target a specific fin, the sample was ion milled to remove material and reach the target site. The milling angle, voltages (acceleration and gun voltage), mill rateandtimewereoptimizedtomin- imize damage and differential milling of the sample surface. The estimated rate of material removal was determined to be 4 nm per min for the acceleration and gun voltages of 100 eV and 500 eV respectively at 10 degrees. Fig. 6 (a) Device layout. (b) Topography image of 14 nm FinFETs prepared by the inverted TEM sample-preparation technique. (a) (b)