February_EDFA_Digital

edfas.org 39 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 1 FA community will need to address how to access the top die, the bottom die, and to test interdependencies, as traditional methods may not work. There was significant audience engagement around this topic throughout the session. Cecile Bonifacio of Fischione Instruments discussed using concentrated Ar ionmilling on only the TEM lamella to remove FIB Ga beam artifacts. It was recommended to use amolybdenumor carbon grid tominimize issues with copper sputtering during broad beam ion milling. Jim Colvin from FA Instruments covered 2.5D/3D access, ultrathin Si, and thermal management. He dis- cussed how these device designs can be challenging for sample prep and how for ultrathin Si, the quality of the underfill is important for stability after thinning. Jim demonstrated successful ultrathinning with iterative RST model measurements to compensate for errors in the polish. There was interest in sample prep for PVC and nano- probing. Jim recommended using a low stress molding compound to re-encapsulate the backside or using dummy Si or underfill for support. Bryan Tracy requested recommendations for a mid- sized, fast band saw that is multimaterial compatible for cutting aluminum around a PCB board. Suggestions included a diamond wire saw, Harbor Freight 3-wheeler tabletop system, water jet cutting, and a Synova water- guided laser cross-sectioning system. Nathan asked Jim to elaborate about the role of RST measurements in the polishing process. Jim explained that RST characterizes thickness uniformity and iteratively added RST maps can help avoid drift in the polish from numerous variables that effect the polish. A participant brought up thinning by course grinding followed by XeF 2 reactive etch on an active device. One caveat mentioned was that submicron polish by this method could erase memory. The next point discussed was that there should be incoming quality checks (like thermal data) prior to thin- ning, tohave confidence that the chipswould likely survive the sample prep process. “THE FA COMMUNITY WILL NEED TO ADDRESS HOW TO ACCESS THE TOP DIE, THE BOTTOM DIE, AND TO TEST INTERDEPENDENCIES, AS TRADITIONAL METHODS MAY NOT WORK.” ISTFA 2021 SYSTEM ON PACKAGE USER GROUP Chair/Co-Chairs: Lihong Cao, Kevin Distelhurst, and Wentao Qin lihong.cao@aseaus.com , kevin.distelhurst@globalfoundries.com, wentao.qin@onsemi.com G reat discussions occurred again this year at the System on Package (SOP) User Group. It was an honor to have the same panelists from last year, including Yan Li from Intel and Susan Li from Infineon, who prompted many of the great discussions. Kevin Distelhurst chaired the session along with Wentao Qin and Lihong Cao, who was unable to attend in person. Ted Kolasa started the sessionwith some general background “THE NEXT POINT DISCUSSED WAS THAT THERE SHOULD BE INCOMING QUALITY CHECKS (LIKE THERMAL DATA) PRIOR TO THINNING, TO HAVE CONFIDENCE THAT THE CHIPS WOULD LIKELY SURVIVE THE SAMPLE PREP PROCESS.” An audiencemember askedwhywater causes delami- nation in bumps. Jim explained that moisture can get absorbed into the package and many of the materials and interfaces are not hermetic, so water can accumulate and cause internal strain. Once the package is removed, the stress dynamics will have changed and delamination can occur. Potting is important to provide stability against water-related stress. The conversation then focused on 3D ICs, which generated a lot of excitement in this User Group session. PowerVia design details, fabrication, and the need for new FA and sample prep solutions were discussed.