February_EDFA_Digital

edfas.org 37 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 1 Susan Li is a director of Failure Analysis Engineering at Cypress Semiconductor Corp., an Infineon Technologies Company. She has more than 25 years of experience and expertise in failure analysis lab operations, failure analysis process, and tools/technique development on micropro- cessor, memory, wired/wireless, and IoT products. Each panelist briefly presented his/her unique thoughts on “Overcoming the Challenges in System-in- Package Failure Analysis.” After all the presentations, the panel discussions were open to questions, comments, and answers among the panelists and the audience about the topic. The enjoyable in-person discussions were open, warm, informative, and constructive, which generated fruitful conclusions for further follow ups in FA Technology Roadmap meetings and ASM Connect user group discussions. Increasing the use of artificial intelligence (AI) to handle complexity was highlighted by all panelists as the most important methodology to overcome SIP FA chal- lenges. Automation and AI applications in imaging tech- niques, for example, optical, SEM, x-ray, and IR can greatly improve FA efficiency. The employment of AI in FA reports by standardizing FA steps, tool names, failed structures, and imaging formats makes it possible to predict results basedonhistorical data. AI adoptions in independent com- ponent analysis (ICA) of signals obtained by fault isolation tools providesmore precise localization ofmultiple failure locations. Followups within the FA community on various AI projects will help facilitate AI utilization and benefit the semiconductor industry. Design and test standardization is crucial for the “design for FA” need tobe consideredduring early product development to ensure effective testing and efficient SIP FA, which can shorten the data feedback loop and ensure timely SIP product launching. Fast nondestructive imaging metrologies, package- level high resolution fault-isolation techniques, and precise sample preparations are the key elements for successful SIP FA. The transition of solder-based inter- connects with ~ 20 µm -1 mm in size and > 20 µm in pitch to Cu-Cu interconnects with a few microns in size and < 10 µm in pitch brings tremendous challenges in bonding qualitymonitoring, nondestructive imaging, interconnect fault isolation, and failure analysis. Technology develop- ment in imaging methodologies, for example 3D x-ray, acoustic, and IR microscopy is urgently needed. Precise package-level fault isolation tools, fast, and artifact-free sample preparation techniques will continuously be the main focuses for SIP FA improvement. Innovation and close collaboration between FA labs and tool vendors “DESIGN AND TEST STANDARDIZATION IS CRUCIAL FOR THE SUCCESS OF SIP FA.” “PRECISE PACKAGE-LEVEL FAULT ISOLATION TOOLS, FAST, AND ARTIFACT- FREE SAMPLE PREPARATION TECHNIQUES WILL CONTINUOUSLY BE THE MAIN FOCUSES FOR SIP FA IMPROVEMENT.” are essential for the success of the entire semiconductor industry. Promoting collaborations in FACouncilmeetings and user group discussions through ASM Connect was commonly agreed upon by the audience. The panel discussions on SIP FA challenges attracted extensive attention from the ISTFA 2021 attendees. The 90-100 minute fully occupied and active discussions pro- vided attendees with plenty of information and new ideas to follow up with in 2022. The FA Technology Roadmap Council and user groups will continue the discussions throughout the year. Please consider sharing your thoughts with us and see you at ISTFA 2022! success of SIP FA. “System-level planning” and “co-design of IC and package” are taking the place of “silicon-centric thinking” in SIP design. SIPs in the current semiconductor device market typically involve heterogeneous technol- ogy integration of dice and components from multiple different companies. Setting up design criterion is vital for test specification and regulation. “Design for test” and