February_EDFA_Digital

edfas.org 25 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 24 NO . 1 the V peak values obtained from forward and backward d C /d V - V signals. Thus, V peak is the point of inflection in the CV data and changes in this value reflect the voltage shift in CV characteristics. As noted, the value of Δ V peak indicates the degree of hysteresis in the data. The reconstructed V peak results obtained from the backward and forward data are shown in Figs. 7a and 7b, while Figs. 7c and 7d respectively provide Δ V peak and D it images acquired from a specimen without POA. These real-space images exhibit an inhomogeneous distribu- tion of clusters, which has been previously observed in local DLTS and SNDM images. The evident variations in the V peak values in Figs. 7a and 7b have been attributed to nonuniform in-plane SiO 2 /SiC interface surface poten- tials. [21] These fluctuations in potential are associatedwith spatially inhomogeneous current and carrier densities in SiCMOS devices. Prior simulations by our group based on actual tr-SNDM D it images have predicted such results. [22] It has also been proposed that a nonuniform interface can potentially result in limited channel mobility. [21,22] Finally, the variations in the Δ V peak values in Fig. 7c reflect a nonuniform distribution of D it . CONCLUSION This article introduced and explained tr-SNDM, a newly developed digital version of SNDM, after briefly discuss- ing the application of conventional analog type SNDM to the assessment of semiconductors. The performance of tr-SNDM was demonstrated by simultaneously acquiring nanoscale local CV, d C /d V - V , and local DLTS data from insulator-semiconductor interfaces. This technique is applicable to the analysis of SiO 2 /SiC interfaces such as those found in power electronics, and the present exami- nation of spatial fluctuations in different images indicates the possibility that intrinsic nonuniformity persists at SiO 2 /SiC interfaces. These results confirm that tr-SNDM is a highly effective technique for the precise quantitative analysis of semiconductor materials and devices, and is superior to conventional analog-type capacitancemicros- copy techniques. REFERENCES 1. Y. Cho, A. Kirihara, and T. Saeki: “Scanning Nonlinear Dielectric Microscope,” Rev. Sci. Instrum., 1996, 67, p. 2297-2303, doi: 10.1063/1.1146936. 2. Y. Cho: Scanning Nonlinear Dielectric Microscopy: Investigation of Ferroelectric, Dielectric, and Semiconductor Materials and Devices, Elsevier, Cambridge, MA, 2020, ISBN 9780128172469. 3. K. Matsuura, Y. Cho, and R. Ramesh: “Observation of Domain Walls in PbZr0.2Ti0.8O3 Thin Film using Scanning Nonlinear Dielectric Microscopy,” Appl. Phys. Lett., 2003, 83, p. 2650-2652, doi: 10.1063/1.1609252. 4. K. Honda and Y. Cho: “Visualization using Scanning Nonlinear Dielectric Microscopy of Electrons and Holes Localized in the Thin Gate Film of a Metal–SiO 2 –Si 3 N 4 –SiO 2 –Semiconductor Flash Memory, ” Appl. Phys. Lett., 2005, 86, p. 013501-1-3, doi:10.1063/ 1.1846147. 5. K. Tanaka and Y. Cho: “Actual Information Storage with a Recording Density of 4Tbit/in. 2 ina Ferroelectric RecordingMedium,” Appl. Phys. Lett., 2010, 97, p.092901-1 -3, doi: 10.1063/1.3463470. 6. K. Ohara and Y. Cho: “Non-contact Scanning Nonlinear Dielec- tric Microscopy,” Nanotechnology, 2005, 16, p. S54-S58, doi: 10.1088/0957-4484/16/3/010. 7. Y. Cho and R. Hirose: “Atomic Dipole Moment Distribution of Si Atoms on a Si(111)-(7×7) Surface StudiedusingNoncontact Scanning Nonlinear DielectricMicroscopy,” Phys. Rev. Lett., 2007, 99, p. 186101- 1-4, doi: 10.1103/PhysRevLett.99.186101. 8. N. Chinone, T. Nakamura, and Y. Cho: “Cross-sectional Dopant Profiling and Depletion Layer Visualization of SiC Power Double Diffused Metal-oxide-semiconductor Field Effect Transistor using Super-higher-order Nonlinear Dielectric Microscopy,” J. Appl. Phys., 2014, 116, p. 084509-1-7, do i: 10.1063/1.4893959. 9. N. Chinone and Y. Cho: “Local Deep Level Transient Spectroscopy using Super-higher-order Scanning Nonlinear Dielectric Microscopy and its Application to Imaging Two-dimensional Distribution of SiO 2 / SiC Interface Traps,” J. A ppl. Phys., 122, 2017, p. 105701-1-9, doi: 10.1063/1.4991739. 10. K. Yamasue, et al.: “Interfacial Charge States in Graphene on SiC Studied by Noncontact Scanning Nonlinear Dielectric Poten- tiometry,” Phys. Rev. Lett., 2015, 114, p. 226103-1-5, doi: 10.1103/ PhysRevLett.114.226103. 11. R. Stephenson, et al.: “Contrast Reversal in Scanning Capacitance Microscopy Imaging,” Appl. Phys. Lett., 1998, 73, p. 2597-2599, doi:10.1063/1.122517. 12. Y. Cho: “High Resolution Characterizations of Fine Structure of Semiconductor Device and Material using Scanning Nonlinear Dielectric Microscopy,” Jpn. J. Appl. Phys., 2017, 56, p. 100101-1-10, doi :10.7567/JJAP.56.100101. 13. Y. Yamagishi and Y. Cho: “Nanosecond Microscopy of Capacitance at SiO 2 /4H-SiC Interfaces by Time-resolved Scanning Nonlinear Dielectric Microscopy,” Appl. Phys. Lett., 2017, 111, p. 163103-1-5, doi: 10.1063/1.4999794. 14. Y.Cho, S. Atsumi, and K. Nakamura: “Scanning Nonlinear Dielectric Microscope using a Lumped Constant Resonator Probe and Its Application to Investigation of Ferroelectric Polarization Distributions,” Jpn. J. Appl. Phys., 1997, 36, p. 3152-3156, doi: 10.1143/ JJAP.36.3152. 15. J. Hirota, K. Yamasue, and Y. Cho: “Profiling of Carriers in a 3D Flash Memory Cell with Nanometer-level Resolution using Scanning Nonlinear Dielectric Microscopy,” Microelectronics Reliability, 2020, 114, p. 113774-1-4 , doi:10.1016/j.microrel.2020.113774. 16. D.V. Lang: “Deep‐level Transient Spectroscopy: A New Method to Characterize Traps in Semiconductors,” J. Appl. Phys., 1974, 45, p. 3023-3032, doi:10.1063/1.1663719. 17. D.W.Cardwell,etal.:“Nm-scaleMeasurementsofFastSurfacePotential Transients in an AlGaN/GaNHigh ElectronMobility Transistor,” Appl. Phys. Lett., 2012, 100, p. 193507-1- 4, doi:10.1063/1.4714536. 18. K. Yamasue and Y. Cho: “Local Capacitance-voltage Profiling and DeepLevel Transient Spectroscopyof SiO 2 /SiC Interfaces byScanning Nonlinear Dielectric Microscopy,” The 28th edition of the IEEE International Symposium on the Physical and Failure Analysis of IntegratedCircuits (IPFA 2021), IEEE, September 14-October 13, 2021. 19. K. Suzuki, K. Yamasue, and Y. Cho: “A Study on Evaluation of Interface Defect Density on High-κ/SiO 2 /Si and SiO 2 /Si Gate Stacks using Scanning Nonlinear Dielectric Microscopy,” 2019 International Integrated Reliability Workshop, IEEE, October 13-17, 2019, doi:10.1109/IIRW47491.2019.8989881. (continued on page 28)