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edfas.org 9 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 The approachwas adjusted todelayer theM4-M1metal layers to account for smearing. Instead of colloidal silica suspension, a Cu polishing slurry solution was employed as the polishing media for CMP. This slurry was primarily colloidal silica with additive 3-amino-1,2,4 triazole, an inhibitor used to balance removal rates of copper and low-k dielectric matrix. [19,20] This slurry reduced smearing and improved surface finish on the lower copper metal layers on the device. Delayeringvia layers V9-V2 involvedwet etchingcopper vias with 49% ferric chloride solution. The 45 nm node fabrication process utilizes a dual damascene process, which requires sputter deposition of a thin Ta/TaN dif- fusion barrier layer on top of copper interconnect layers to prevent Cu diffusion into the ILD. [21] Ferric chloride has high selectivity for copper metal over Ta/TaN, which acted as an etch stop to prevent over-etching into lower copper layers. The resulting surfacewas a layer of ILDwith empty via holes, which were imaged and extracted with the secondary electron detector in the SEM. The W poly- silicon contact vias, acting as an etch stop, were exposed by etching the M1 copper with ferric chloride. The optical images of the test article at exposed layers M11-V2, M1, and the polysilicon contact vias in the region of interest can be seen in Fig. 5. All of the samples and layers shown in Fig. 5 were prepared with CMP and wet etching. Wet etching to delayer and expose V1 was not a viable method in this approach. Due to theminimal thickness of the V1 layer, secondary electron imaging offeredminimal contrast between via holes and dielectric. The tungsten polysilicon contact vias underneath M1 also produced undesirable noise in the backscattered electron (BSE) detector imagedue to thehighatomicnumber of tungsten, causing contrast interference from underneath. To over- come this challenge, the V1 layer was backside delayered for imaging with the copper metal intact. To delayer down to V1, the samplewasmounted back- side in a bed of epoxy on a SEM stub, and the bulk silicon on the diewas thinned to approximately 70 µmremaining silicon thickness (RST). The bulk silicon was then etched in the XeF 2 vapor etcher as described previously. The BOX layer underneath the active region on the device acted as an etch stop, protecting features deeper in the circuit. After exposing the BOX layer on the backside, the P-FIB was used to mill the region of interest to expose the M1 copper. The P-FIB delayering was done over an area of 50,000 μm 2 with an accelerating beam voltage of 30 kV and apertures of 1.0, 4.0, and 15.0 nA. Apertures were selected with regards to the remaining amount of mate- rial to the target and desired surface finish. [22] Using these settings, the dual beam P-FIB was used to iteratively mill approximately 50 nm depth at a time, equating to 10 to 15 minutes per step. Between delayering steps, SEM was used to observe the resulting surface and determine the next processing steps and the delayering endpoint, similar to the iterative CMP process. Due to different sputter rates between copper and ILD, gas-assisted injection of methyl nitroacetate was used to balance the disparate removal rates so that the surface could be evenly milled to expose M1. After theM1 copper layer was exposed, the devicewas removed fromtheP-FIBandwet etchedwith ferric chloride to strip the metal, as in via layers V9 through V2, but from the backside. The Ta/TaN diffusion barrier between M1 Fig. 5 Optical micrographs of 45 nm SPI test article samples delayered to specific layers, all using CMP and/or wet etching techniques.