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edfas.org 7 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 nanometers, features under 1 µm in size are challenging to observe. SCANNING ELECTRON MICROSCOPY Within a delayering framework, the SEM is used for observation of features unresolvablewithOMand ismore common to observe layers in advanced technology node devices. Dedicated image acquisition systems are used for scanning high resolutionmosaics of entire IC layers for full design file recovery, but desktop systems are useful for fast observation and imaging areas of interest during delayer- ing. Conductive silver paint and sputtered gold coatings on samples reduce electron beam induced charging. For the 45 nm decomposition, samples were observed in a desktop SEM between delayering steps to determine if a given layer showed features with sufficient brightness, contrast, and pixel separation with backscatter electron or secondary electron signals. If all conditions were met, the samplewasmosaic imaged in a chip scanning SEM for full target layer capture. ENERGY DISPERSIVE SPECTROSCOPY Energy dispersive spectroscopy is used during the delayering process for qualitative elemental identification on an IC surface or cross section. The technique is useful for general identification of unknown materials or debris onan IC thatmay appear duringdelayering. The technique can also give insight to the composition of metal features anddielectric layers, which canhelp identifymaterials and etch stops required for wet and dry etching techniques. However, due to the thinmaterial layers on an IC, the tech- nique is limited in use for quantitative surface elemental identification. 45 nm SPI DEVICE COMPOSITION AND MATERIALS The 45 nm SPI device for consideration consists of 11 metal layers, 10 via layers, a polysilicon contact layer, a polysilicon layer, and an active silicon layer, shown in Fig. 2. The topmetal layer, M11, is aluminumand covered with a silicon nitride passivation layer. All other metal layers consist of copper metal features in a matrix of interlayer dielectric (ILD). V10 ismadeof tungsten through- vias in an ILD matrix. Via layers V9-V1 comprise copper through-vias in a matrix of ILD. Four different materials function as ILD on this device in the stack: silicon dioxide (SiO 2 ), fluorinated tetraethyl orthosilicate (F-TEOS), a proprietary porous low k-value dielectric, and a low-k SiCOHdielectric. [14] The polysilicon contact layer contains tungsten through-vias aswell as the polysilicon and active layers consist of silicon based features. Underneath the active Si layer, is a buried oxide (BOX) layer made of SiO 2 , approximately 145 nm in thickness. As part of the sample preparation framework pre- sented, each individual feature layer shown in Fig. 2 was delayered and SEM mosaic imaged in the region of inter- est (ROI). The ROI, the target SPI module, is highlighted in Fig. 3. The region is approximately 500 x 100 μm. 45 nm IC DELAYERING FRAMEWORK The approach taken for sample preparation of the 45 nm SPI involved using specific delayering methods to expose layers with sufficient contrast in order to use SEM imaging. Following that, vector-based polygons of the features oneach layerwereextractedusing imageanalysis. By combining the extracted polygon sets for each imaged layer, the full design of the device was reconstructed. Examples of the processes following delayering are shown in Fig. 4, which led to the final polygon reconstruction of the entire device stack. Table 1 shows the delayering approach taken for spe- cific groups of layers based on the material, ILD material, thickness, and smallest feature size of each individual layer. Often, when GDSII layers have similar features sizes, thicknesses, ormaterials, some delayeringmethods proved useful to expose several layers at once. RESULTS Referring to Table 1, the M11 layer contains the largest and thickest features. M11 is not planarized during the fabrication process, so CMP with a flat, aggressive abra- sive such as diamond lapping filmquickly planarized and exposed the layer for SEM imaging and GDSII polygon extraction. If anything besides DLF was used, such as a polishing pad and slurry, the nonplanarity of the initial surface would have propagated through subsequent layers, leading to issues such as edge rounding. M10 through M5, consisting of Cu, were polished with 50 nmcolloidal silica suspension. The alkaline suspension preferentially polished through ILD covering each metal layer. Copper was slow polishing against colloidal silica, so this method of CMP could expose higher copper metal layers in a controllable manner. Below M5, CMP with Fig. 3 Opticalmicrographof unprocessed45nmtest article, highlighting the SPI, which is the region of interest.