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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 6 a high vacuum chamber. The resulting reactions form gaseous or high vapor pressure species which are then promptly removed via vacuum exhaust. RIE offers highly selectivematerial removal inside of awell-controlled envi- ronment. The high vacuum chamber minimizes material redeposition. Process parameters such as background gas pressure, gas mix, gas flow rates, power, and platen temperature can be adjusted to control etch rates. RIE systems can use stage biasing to enhance anisotropic etching behavior. As a delayering technique, RIE can be limited by the material of interest particularly if it can contaminate RIE chambers, such as copper, making it difficult to use for fabrication intended systems. The P-FIB is a state-of-the-art dry etching tool that sources ions froma xenon plasma, offering higher current output than conventional galliumsources. For delayering, this tool is used for milling evenly across targeted regions of interest on the sample. Samples are delayered in a high vacuum environment with a xenon ion column and can be observed using an in-situ SEM. Gas-assisted injection systems implemented with the tool can enhance milling rates, such as xenon difluoride (XeF 2 ) gas injection for silicon milling and methyl nitroacetate to balance milling rates between copper and dielectric materials. This tool is limited in the area it can delayer by the ion beam’s horizontal field width (HFW) of 1.85 mm. As in a standard focused ion beam (FIB) tool, a P-FIB can also be used for cross sectional milling to ascertain specific layer thick- nesses on an IC. VAPOR ETCHING Vapor etching, or gas-etching, includes material removal with vapor. The XeF 2 vapor etch is a delayering method to etch bulk silicon for the utility of backside delayering. With theoretical etch rates of 40 μm per minute, XeF 2 can remove the entirety of the bulk silicon of a device quickly, allowing for direct backside access to the device. [11] XeF 2 also has a high selectivity for Si versus silicon dioxide (SiO 2 ), so buried oxide (BOX) layers in silicon-on-insulator devices act as etch stops to ensure active transistor features are preserved. [12] Without an etch stop, the XeF 2 etches away all silicon features on the device backside. METROLOGY Observationof the IC surface is paramount to interpret- ing results from IC material removal techniques. Optical microscopy (OM) and scanning electron microscopy are two common techniques used for this. SEM is also used for imaging FIB cross sections to determine IC layer thicknesses. Energy dispersive spectroscopy (EDS) can be used for elemental identification on sample surfaces and provides critical assessment of thematerial composi- tion when developing a new process for an uncharacter- ized sample. OPTICAL MICROSCOPY The optical microscope is the standard observation tool used during delayering processes in this framework. Optical images are takenbetweendelayering steps primar- ily to depict material-based changes that occur during CMP and wet/dry etching processes, as well as to create a referenceable record of process results. Seeing that the dielectric film thickness is a function of color, optical images provide critical data for determining delayering endpoints and guiding further processing. [13] By determin- ing the pattern or direction of material removal through OM image comparisons, CMP parameters can be adjusted to modulate material removal rates. While the diffraction limited resolution of an OM is on the order of hundreds of Fig. 2 45 nm SPI test article STEM cross section.