November_EDFA_Digital

edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 4 EDFAAO (2021) 4:4-13 1537-0755/$19.00 ©ASM International ® A SAMPLE PREPARATION WORKFLOW FOR DELAYERING A 45 nm NODE SERIAL PERIPHERAL INTERFACE MODULE Yash Patel 1 , Joshua Baur 1 , Jonathan Scholl 1 , Adam R. Waite 1 , Adam Kimura 1 , John Kelley 1 , Richard Ott 2 , and Glen David Via 2 1 Battelle Memorial Institute, Columbus, Ohio 2 Air Force Research Lab, Dayton, Ohio pately@battelle.org INTRODUCTION The growth of the semiconductor industry over the last couple of decades has caused the design and manu- facturing process formicroelectronics to become global in nature, creating very complex and opaque supply chains. A typical semiconductor productionprocess spans several countries, multiple states, and makes numerous trips around theworld. [1] For this reason, it is extremely difficult to ascertain the quality and integrity of manufactured chips with any level of confidence. This is a significant concern for end use applications that require highest levels of reliability and assurance. For example, a satellite system is only deployed once and requires all of its components to last through- out the life of the satellite. An unreliable or failed component could result in a compromised or nonfunctional system. Microelectronics inserted into critical defense systems likewise require high levels of assurance that the component will func- tion exactly as intended and not add or remove any functionality. In recent years, new areas of post-fabrication verification and validation have been developed toaddress theseproblems and toprovidemecha- nisms for assessing untrusted microelectronics that were fabricated in an insecure offshore foundry. [2,3] This verification process involves the full delayering of the integrated circuit chip and imaging each layer of the manufactured design. Each target layer then has metal traces, vias, assorted front end of line features that are extracted from raster images and converted into vectorized polygons. After the polygons have been extracted, the as-fabricated layout and netlist design files can be recovered for comparing against the golden reference design. InKimura et al., [5] this process was demonstrated on a 130 nm serial peripheral interface (SPI) modulewhere the chipwas fully delayered and design files recovered. Many of the sample delayering and imaging techniques applied towards post-fabrication microelectronics assurance have been leveraged from the failure analysis community, as discussed in Kimura et al. [4] As these approaches start to target more advanced technologies atmodern technology nodes, the techniques that were used at the larger legacy nodes become less Fig. 1 Flowchart overview of delayering workflow and associated techniques.