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edfas.org 37 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 Rev. Appl., 2014, 1, p. 024004. 12. P. Maunz: “High Optical Access Trap 2.0,” SAND2016-0796R, 2016. 13. M. Revelle: “Phoenix and Peregrine Ion Traps,” arXiv:2009.02398, 2020. 14. R.C. Sterling, et al.: “Fabrication and Operation of a Two- dimensional Ion-trap Lattice on a High-voltage Microchip,” Nature Communications, 2014, 5, p. 3637. 15. G. Harman: Wire Bonding in Microelectronics, 3/e, McGraw-Hill Education - Europe, 3rd ed., 2010. 16. B. Selikson and T. Longo: “A Study of Purple Plague and its Role in Integrated Circuits,” Proceedings of the IEEE, 1964, 52 (12) p. 1638–1641. 17. R.C. Blish, et al.: “Gold–Aluminum Intermetallic Formation Kinetics,” IEEE Trans. Device Mater. Rel., 2007, 7 (1) p. 51–63. 18. J.B. Hertzberg, et al.: “Laser-annealing Josephson Junctions for Yielding Scaled-up Superconducting Quantum Processors,” arXiv:2009.00781v4 [quant-ph], 2020. multi-die interconnect bridge (EMIB) was developed so the high-density connection is placed only where needed, between the dies that need to communicate with chiplets such as a logic die, transceivers, and HBM. With EMIB the substrate supplier places a high- density silicon bridge in a laminate substrate. With Intel’s new GPU, Foveros tiles and HBM stacks are connected using EMIB. Intel refers to this as co-EMIB. [1] Companies including ASE, Amkor, SPIL, and TSMC have introduced fanout on substrate options for chiplets. TSMC has demonstrated a 51 x 42 mm area with five redistribution layers (RDLs) on a 110 x 110 mm substrate. A 36 µm die-to-die I/O pitch has been demon- strated. [1] TSMChas shown that 3Dsolutions usingdirect bonding to connect pads without bumps result in higher intercon- nect bond density. This allows the chip designer flexibility and extensibility on designing a newchip and new system device, adopting the most advanced integration tech- nology for cost and performance advantages. Electrical resistance is lower because there is no solder bump. Lower insertion loss is also reported. High-quality signal integrity and power integrity with low RC delay and low IR drop are also reported. Energy consumption/bit is lower (as measured in pJ/bit) and thermal resistance is lower. This means less energy is required to move data around. With a fixed power envelope, less energy spent per bit means that more bits can be transferred or that the saved energy can be spent on other resources. [1] Later this year, AMDwill introduce a SRAM stacked on a processor and connected with bumpless or hybrid bonding. CHALLENGES The chiplet strategy is not without its challenges and associated cost. Packaging chiplets is expensive. Co-design is a must. Chiplet IP blocks must be able to communicate with each other. There is no standard die- to-die interface solution on the market today, instead proprietary solutions are used. Careful thermal analysis is important, especially with 3D stacking. Hybrid/bumpless bonding requires a clean surface for bonding and a clean environment. Particles will result in failures. New test and inspection methods are needed. These challenges are not insurmountable and an increasing number of chiplet solutions are entering the market. ABOUT THE AUTHOR E. JanVardamanispresidentandfounderofTechSearch International Inc., which has provided market research and technology trend analysis in semiconductor packag- ing since 1987. She is the author of numerous publications on emerging trends in semiconductor packaging and assembly. She is a senior member of IEEE EPS and an IEEE EPS Distinguished Lecturer. She received the IMAPS GBC Partnership award in 2012, the Daniel C. Hughes, Jr. Memorial Award in 2018, the Sidney J. Stein International Award in 2019, and is an IMAPS Fellow. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corp., the electronics industry’s first precompetitive research consortium. GUEST EDITORIAL CONTINUED FROM PAGE 2 Fig. 1 Foveros technology in Samsung Galaxy Book S.