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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 32 a trapping node located 30-100 µmabove the trap surface. Because the control electrodes act as RF ground, this creates a quadrupole field which is perpendicular to the RF electrode and the trap surface, and allows for an ion to be trapped (see Fig. 3). [8] Several species of ions are well suited to QIS, but for the heaviest such as ytterbium (Yb+) and barium (Ba+), 200-300 V at frequencies of typically 50-100MHz is applied to the RF electrodes. However, with any ion only 1-10 V is required on the control electrodes to create the axial confinement. MICROFABRICATED ION TRAP DEVICES AND PACKAGING While there are many methods for constructing an ion trap for QIS experiments, [9] the ion trap chips used in the failure examples discussed here are constructed on silicon (Si) substrates using both very large-scale inte- gration (VLSI) integrated circuit andmicroelectromechan- ical systems (MEMS) device integration techniques. [10] The common techniques of thin-film deposition, pho- tolithography, subtractive etching, and bulk and surface micromachining methods are employed to render an ion trap chip having many attributes similar to electronic devices. Importantly, the CMOS-inspired back-end-of-line (BEOL) topology enables nearly arbitrary trap electrode geometries. MEMS processing techniques are used to create through-holes and nonrectilinear shapes in the Si chip for ion loading andmicro-optics integration. [11] Post- fabricationwet etches remove insulating oxide fromunder the edges of and between trap electrodes and singulate trap devices from the Si wafer substrate. The realization of arbitrary chip shapes, such as the bowtie shaped high optical access (HOA) trap chip platform in Fig. 2 [12,13] is enabled by deep Si etching, which is also used for on-chip, high value capacitors for RF voltage shunting. In contrast tomost electronic devices, surface ion traps must support RF amplitudes greater than 300 V to define the trapping fields. This demands relatively thicker inter- metal dielectric (IMD) films (2-8 µm of SiO 2 ) to prevent RF breakdown [14] and thicker metal layers (1.4 and 2.8 µm of Al-½%Cu) to lower resistance and capacitance and there- fore ohmic power dissipation. Stresses from the variable combinations of these thicker films can affect device yield (loss due to cracking and film delamination) especially during the singulation process. Other characteristics unique to microfabricated ion trap chips are a) themethod of die singulation from the Si substrate, b) the inability to identify known gooddie (KGD) prior to packaging, c) the lack of a contact probe method to identify open circuit electrodes, plus d) an incredible sensitivity to surface contaminants and outgassing. The ideal way to validate an ion trap device is to trap an ion, however this type of functional test is impractical due to the high cost in both time and materials. Reduction of defects is critical to increasing the likelihood of a good ion trap. A principal challenge is minimizing the device handling as defects can occur during any processing step such as fabrication, release (removal of oxide fromaround the electrodes), singulation, assembly/packaging process, and trap installation. This puts a premiumon high quality visual inspection (optical and electron imaging) to detect defects, both before packaging and post-packaging prior to device use. Optically good dies are attached using solder or epoxy to ceramic packages. Attachment failures during shipping and use, for example upon cool down to cryogenic tem- peratures, emphasize the importance of the trap-package assembly for QIS experiments. Wire bonding failures such as misplaced bonds have been encountered and these sometimes arise due to special trapping requirements, for example lowering loop heights to a few tens of microm- eters to avoid interference with trapping lasers by using a wedge bonder. These issues also highlight the importance of co-design of the trap chip and package. DETECTING SHORTS AND OPENS IN ION TRAP ELECTRODES Trapping ions and then cooling theminto theirmotion- al ground state calls for all electrodes of the ion trap (other than the RF) to be pinned at a specific potential, whether to ground or to a control voltage value. Control electrodes are specifically used to create or shim the local trapping Fig. 3 Illustrative cross section of a linear surface trap demonstrating the electric fields lines. This electrode geometry creates a quadrupole field which time averages to create a potential minimum, where the ion is trapped, and a trapdepth of several times room temperature. The ion moves slightly in the trap as a functionof timeas the trap shape changeswith theRF frequency, resulting in radialmicromotion. Assuming the ion is well aligned to the RF minima, then the micromotion is small compared to the temperature of the ion. FAILURE MODES IN MICROFABRICATED ION TRAP DEVICES (continued from page 29)