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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Madrid Tramble Production Supervisor Joanne Miller Managing Editor Victoria Burt Contributing Editor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh GlobalFoundries Singapore Ted Kolasa Northrop Grumman Innovation Systems Rosalinda M. Ring Howard Hughes Research Labs LLC Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright©2021by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $160 U.S. per year. Authorization tophotocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registeredwith theCopyright ClearanceCenter (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly toCCC, 222 RosewoodDrive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. N ew packaging solutions are being adopted to achieve the economic advantages that were pre- viously met with silicon scaling. The role of het- erogeneous integration, especially chiplets, is pivotal in this newera. The Taiwan Semiconductor Manufacturing Company (TSMC) indicates that the use of chiplets will be one of the most important developments for the next 10 to 20 years. The adoption of chiplets represents an inflection point in IC design for CPUs and GPUs; similar to the transition from perimeter pad design to area array with the adoption of flip chip interconnect. WHAT IS A CHIPLET? A chiplet is a functional circuit block and includes reusable IP blocks. It is a physically realized and tested IP with a standard or proprietary commu- nication interface between IP blocks. A chiplet functions with other chiplets, so the design must be co-optimized, and the silicon cannot be designed in isolation. A chiplet can be created by partitioning a die into functions and is typically attached to a silicon interposer or organic substrate today, but new options are emerging such as advanced fanout, RDL interposer, embedded bridges, and 3D stacking. The close cooperation between all segments of the industry, EDA tool vendors, IC designers, third party IP providers, foundries, andOSATs will help drive the growth of chiplets into a wide range of applications. DRIVERS FOR CHIPLET ADOPTION An increasing number of companies are turning to chiplets to achieve the economic advantages lost with expensive monolithic scaling, ushering in a newera of smart packaging. AMD indicates that themajor drivers for its adop- tion of chiplets include risingmanufacturing cost for large dies, increased cost of mask sets, increased complexity of design rules in leading-edge nodes, and architectural challenges of meeting relentless demand for increased compu- tational power. [1] Cost savings can be obtained by partitioning dies and only fabricating the logic functions on the most advanced nodes where needed most. Smaller dies also result in higher yield per wafer, resulting in savings. AMD also notes that with chiplets it is possible to have higher core counts and therefore higher performance than with a monolithic design. Binning the chiplets provides an opportunity to optimize performance even further. Intel has introduced Foveros technology as a chiplet solution in which a logic die fabricated on an advanced 10 nm node is connected to a base die containing I/O and other functions. The base die is fabricated in a less advanced 22 nm node. Intel refers to chiplets as tiles. Intel’s embedded NOVEMBER 2021 | VOLUME 23 | ISSUE 4 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL CHIPLETS: A NEW ERA IN ADVANCED PACKAGING EMERGES Jan Vardaman, TechSearch International Inc. jan@techsearchinc.com edfas.org Vardaman (continued on page 37)