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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 4 10 and V1/M2 acted as an etch stop. The resulting layer was a field of V1 viaswith coppermetal intact, allowing for BSE imaging with the SEM, as shown in Fig. 6. The polysilicon and active Si layers were delayered with a similar method. The features on these layers were 65 nm thick and 80 nm thick respectively, and therefore could not be exposedwithmore aggressivemethods such as CMP due to concerns of over polishing features. The sampleswere backside epoxymounted and XeF 2 etched in the samemanner as the V1 sample. After etching the bulk silicon, the samplewas P-FIBmilledwith the same settings and methods to both polysilicon and active Si layers, as shown in Fig. 7. Because the material on the active and polysilicon layers consisted of Si and SiO 2 , methyl nitro- acetate gas injection was not required, and this layer was exposed with only xenon ion milling. CONCLUSION In this work, a framework for the sample preparation for delayering a 45 nm SPI was presented. The device, consisting of 24 feature layers, was delayeredwith topside CMP methods and wet etching with additional utilization of dry etching techniques. The techniques discussed in this work were built upon previous methods used to delayer a 130 nm node device region of interest [2] and are further developed to the more advanced 45 nm node, where a minimum feature size of 40 nm proved challenging for techniques such as CMP and wet etching. As features decrease in size, the success of SEM imaging and feature extraction for design validation will be contingent on reli- able sample preparation methods. Encountering these challenges resulted in the development of processing techniques for delayering using P-FIB, backside Si etching, and selective chemical slurries. These methods will be critical going forward for delayering advanced node tech- nology where feature sizes are continuously decreasing, and features become more difficult to image. ACKNOWLEDGMENTS This work was sponsored by the Air Force Research Laboratory inDayton, Ohio in support of theOUSDTrusted and Assured Microelectronics (T&AM) program. The authors would also like to thank Eric Udelhoven for the imaging of the STEM cross section of the device. DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Approval ID: AFRL- 2021-2035. REFERENCES 1. Semiconductor Industry Association: Nathan Associates, Beyond Borders: The Global Semiconductor Value Chain, semiconductors. org, May 2016. 2. A. Kimura, et al.: “A Decomposition Workflow for Integrated Circuit Verification and Validation,” Journal of Hardware and Systems Security, DOI: 10.1007/s41635-019-00086-6, 2019. Fig. 6 Backscatter electron SEM images of polysilicon (left) and active (right) regions on the ROI exposed by P-FIB delayering. Fig. 7 BSE SEM image of V1 subregion exposed by P-FIB milling and wet etching from the backside. (continued on page 12)