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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 40 NOTEWORTHY NEWS NANOTS 2021 The 41st NANO Testing Symposium (NANOTS 2021) will be held October 25-27 at KFC Hall, Kokusai Fashion Center, in Tokyo. NANOTS is one of the leading technical symposiums for discussing solutions that improve the testing process of nanoscale devices and materials. NANOTS is sponsored by the Institute of NANO Testing in cooperation with the Institute of Electronics, Information and Communication Engineers, the Japan Society of Applied Physics, the Reliability Engineering Association of Japan, and the Union of Japanese Scientists and Engineers. For more information, visit the NANOTS website at www-nanots.ist.osaka-u.ac.jp/en. GUEST EDITORIAL CONTINUED FROM PAGE 2 opportunities for innovative partitioning in all three dimensions. Anumber of interestingproducts andproduct demonstrations, announced in recent years, including on-package integration of high-performance field-pro- grammable gate arrays (FPGA) die, advanced analog to digital converters/digital to analog converters (ADC/DACs), optical-electrical chips, highbandwidthmemory,modular graphics processing unit (GPU) and central processing unit (CPU) tiles have taken advantage of advanced pack- aging architectures. Some of these demonstrations have been facilitated by the availability of advanced interface bus (AIB), an open-sourced high bandwidth, high power efficiency IO specification that makes “plug-and-play” modular integration possible. In the bigger picture, wide- ranging collaborative efforts involving industry, academia, various research consortia and technical professional organizations are in place today to establish and refine a roadmap for the evolution of heterogeneous integration technologies. One such roadmap that has sponsorship from three IEEE societies, SEMI, and one ASME division, and the participation of many industrial practitioners and academic partners, clearly shows the opportunities and challenges of heterogeneous integration not only in advanced packaging for high performance computing but also acrossmultiple applications includingmedical, wear- able, automotive, Internet of things (IoT), and aerospace devices. As increasingly diverse functionalitywill continue to be integrated on package substrates, the packaging community will be challenged across multiple fronts including power delivery, high-speed signaling, materials, design for performance/cost/reliability/manufacturability and thermal management. We will need to develop new methods of debug, failure analysis, and fault isolation to ensure we keep pace with this rapidly evolving field. However, all these challenges are also opportunities for increased innovation and promise an exciting time ahead for this field. ABOUT THE AUTHOR Ravi Mahajan is an Intel Fellow responsible for assem- bly and packaging technology pathfinding for future silicon nodes. Mahajan also represents Intel in academia through research advisory boards, conference leadership, and participation in various student initiatives. He has led pathfinding efforts to define package architectures, technologies, and assembly processes for multiple Intel silicon nodes including 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, and 7 nmsilicon. Mahajan joined Intel in 1992 after earning his Ph.D. in mechanical engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost- effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. He is one of the founding editors for the Intel Assembly and Test Technology Journal andcurrently vicepresident of publica- tions andmanagingeditor-in-chief of the IEEETransactions of the CPMT. Mahajan is a Fellow of two leading societies, ASME and IEEE.