Aug_EDFA_Digital

edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 34 PREVIEW A fter a very long year of lockdown, remotework, and video conferencing due to the COVID-19 pandemic, the 47th International Symposium for Testing and Failure Analysis (ISTFA) has been planned as an in-person event to be held in Phoenix in 2021 from October 31 to November 4. The theme this year will be “Riding the Wave of System in Package (SIP).” In the 21st century, the electronic market will be driven by consumers with demands of immediate entertainment, fast access to infor- mation, and communications anywhere in a personalized fashion and at affordable prices. The new challenge is not how many transistors can be built on a single chip as in SOC (system on chip), but rather how to integrate diverse circuits together predictably, harmoniously, and cost effectively. Instead of getting twice the transistors for the same cost as Moore’s Law predicted in the past 50 years, ISTFA 2021 Susan Li, ISTFA 2021 General Chair Infineon Technologies Susan.Li@Infineon.com the goal of SIP is to obtain the same number of transistors for half the cost within less than half the time to market. To further understand the roadmap from advanced packaging for heterogeneous integration to future SIP development, our keynote speaker will be Dr. Ravi Mahajan, Intel Fellow and lead architect for packaging technology architecture, assembly & test technology. Dr. Mahajan is responsible for planning and carrying out multi-chip package pathfinding for the latest process technologies since joining Intel in 2000. He is an IEEE EPS Distinguished Lecturer, and a Fellowof two leading societ- ies, ASME and IEEE. The panel discussion will expand upon the keynote speech by focusing on “Overcoming the Challenges in System in Package Failure Analysis.” Discussion points will include SIP fault isolation and failure analysis gaps The Phoenix Convention Center.