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edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 2 PURPOSE: To provide a technical condensation of information of interest to electronic device failure analysis technicians, engineers, and managers. Nicholas Antoniou Editor/PrimeNano nicholas@primenanoinc.com Scott D. Henry Publisher Mary Anne Fleming Manager, Technical Journals Toby Hansen Production Supervisor Joanne Miller Managing Editor Victoria Burt Contributing Editor ASSOCIATE EDITORS Navid Asadi University of Florida Guillaume Bascoul CNES France Felix Beaudoin GlobalFoundries Michael R. Bruce Consultant David L. Burgess Accelerated Analysis Jiann Min Chin Advanced Micro Devices Singapore Edward I. Cole, Jr. Sandia National Labs Szu Huat Goh GlobalFoundries Singapore Ted Kolasa Northrop Grumman Innovation Systems Rosalinda M. Ring Howard Hughes Research Labs LLC Tom Schamp Materials Analytical Services LLC David Su Yi-Xiang Investment Co. Paiboon Tangyunyong Sandia National Labs Martin Versen University of Applied Sciences Rosenheim, Germany FOUNDING EDITORS Edward I. Cole, Jr. Sandia National Labs Lawrence C. Wagner LWSN Consulting Inc. GRAPHIC DESIGN Jan Nejedlik, designbyj.com PRESS RELEASE SUBMISSIONS magazines@asminternational.org Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- lished quarterly by ASM International ® , 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. org. Copyright©2021by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS membership. Non-member subscription rate is $160 U.S. per year. Authorization tophotocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by ASM International for libraries and other users registeredwith theCopyright ClearanceCenter (CCC) Transactional Reporting Service, provided that the base fee of $19 per article is paid directly toCCC, 222 RosewoodDrive, Danvers, MA 01923, USA. Electronic Device Failure Analysis is indexed or abstracted by Compendex, EBSCO, Gale, and ProQuest. Microelectronics packaging has come a long way in the past several decades, with its function having evolved fromprimarily providingmechanical protection along with (limited) interconnectivity, to becoming a critical enabler of cost effective, reliable performance of semiconductor devices. This evolution has been shaped by the need for cost-effective solutions that meet chal- lengingperformance,manufacturing, schedule, environmental, and systemfit requirements ina rapidly diversifying application environment. In thepast few years there has been increasing interest in advanced package architectures as compact, high performance platforms for heterogeneous integration (HI) across a wide variety of computing and communication applications. This increased interest in advanced packaging is primarily driven by four needs: 1) for increasedon-packagebandwidth, 2) to integratediverse IP frommultiple foundries, 3) for improved yield resiliency, and 4) to meet time-to-market demands. A number of innovative package architectures that enable power- efficient, on-package bandwidth interconnects and make major advances in microelectronics performance possible, have proliferated in themainstream of semiconductor packaging. Advanced packaging architectures, for example embeddedmulti-die interconnect bridge (EMIB), chip-on-wafer-on-substrate (CoWoS), Foveros, and co-EMIB (Fig. 1) in conjunctionwith traditional organic packaging technologies today offer product architects a wide technology envelope for interconnect density that can be used to deliver innovative products. EMIB, CoWoS, and co-EMIB use silicon backend wiring technolo- gies to deliver high density lateral connections which are complemented by high density vertical connections between stacked die in Foveros, CoWoS, and co-EMIB. These advanced packaging architectures open up significant AUGUST 2021 | VOLUME 23 | ISSUE 3 A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS ELECTRONIC DEVICE FAILURE ANALYSIS GUEST EDITORIAL ADVANCED PACKAGING FOR HETEROGENEOUS INTEGRATION Ravi Mahajan, Intel Corporation ravi.v.mahajan@intel.com edfas.org Mahajan Fig. 1 Advanced packaging technology portfolio. (continued on page 40)