Aug_EDFA_Digital

edfas.org 1 1 ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 necessary because the transistor implementation is fully differential. So, the input signal has to be differential as well. The coupler block shows two output signals on the right that are provided by Cadence. The signals are the pulse density modulation signal y of the modulator and themain clock signal. They forma sample and hold block, whichwrites the outputs to theMATLABworkspace, where it can be processed. A corresponding coupler schematic is also inserted in the test bench of the modulator in Cadence shown in Fig. 7. The labels on the leftof this block are called outputs because they come from Simulink and are connected to the inputs vin+ and vin− of the schematic. On the other hand, the output y of the modulator is connected on the right of the coupler block, where the label of the block indicates the input to Simulink. There are two additional preparation steps: first, a netlist has to be generated for simulation of the modu- lator with the Cadence simulator Spectre; second, a simulation run script is created for the modulator test bench via the simulation environment. This run script is called by Simulink. [7] The run script changes the path setting to the netlist and executes the simulation. After the co-simulation, the output spectrum is built and com- pared with the Simsides model. The comparison of the analog full-schematic simulation and the system model is depicted in Fig. 8. The spectra have been smoothed to analyze the differences. Looking at the comparison, two main differences between the full-schematic and the system model can be observed. The first one is the increased noise floor for lower frequencies. This is a result of the limited gain of the operational amplifiers because the transistor ampli- fiers are not ideal. On the other hand, the Simsidesmodel assumes an unlimited gain and assumes a lower noise floor as a result. This has the effect that the real SNR is limited at 59 dB. Equation 1 yields an effective resolution of 9 bit. The second main difference between the full-sche- matic and the system model is the occurrence of higher harmonics in the transistor version. Primarily, the third and fifth harmonic of the input signal are observed in the output spectrumat normalized test frequency of 1.5×10⁻ 2 and 2.5×10⁻ 2 in Fig. 8. This is a result of the nonlinearity of theoperational amplifiers. Increasing thegain-bandwidth- product would help to solve this problem. Another pos- sibility is to sample the input at a lower sampling rate, but thiswould strongly affect the bandwidthof themodulator. CONCLUSION The co-simulation techniquewas successfully applied by the comparison of a full-schematic design to a system model. A second order ΔΣ modulator has been designed in XFAB’s XH018 technology while the system model has been created in MATLAB/Simulink. In the example, the design is achieved in two steps, the system model from the ΔΣ toolbox is rebuilt in the Simsides model to obtain amplifier coefficients that are reused in the schematic. Except for the clock generation and the reference voltages, all circuit elements are rebuilt in the schematic within Virtuoso. The co-simulation of the full-schematic design shows two deviations in comparison to the systemmodel. A SNR of only 59 dB instead of 70 dB is obtained for low frequen- cieswhich gives only an effective resolution of 9 instead of 11 bits. Additionally, non-linearities have been detected, which proves the applicability. Thus, the co-simulation technique presents the possibility to build larger Simulink system models and replace parts of it with its transistor model or even a reannotated physical equivalent. Also, failuremodels can be easily verified of falsified by adapta- tion of the systemmodel and easier simulation. Fig. 8 Comparisonof theoutput spectraof theco-simulation (red) and the Simsides model (blue). Fig. 7 Implementation of the co-simulation in Virtuoso.