Aug_EDFA_Digital

edfas.org ELECTRONIC DEV ICE FA I LURE ANALYSIS | VOLUME 23 NO . 3 10 model, the spectrumof the output signal is comparedwith the abstract system model. As no significant differences are found, the Simsides model and the capacitor ratios are assumed to be correct. Both spectra can be seen in Fig. 5. A signal-to-noise ratio of 69.8 dB is extracted from the data at the normalized test frequency of 5×10⁻ 3 , which fits nicely to the ΔΣ toolbox results. TRANSISTOR CIRCUIT DESIGN The design of the transistor model is done in Cadence Virtuoso IC6.1.7. The XH180nmprocess fromXFAB is used in the XKIT design environment. All circuit elements are designed with library elements of this process except for the clock generator and the reference voltages. The circuit elements are the operational amplifiers, a comparator with a RS-latch, the bias circuit, logic gates and transmis- sion gates as switches. The implementation of the circuit is fully differential and resembles the design proposal in de la Rosa and del Río. [3] Themain part of the switched capacitor integrator are two operational amplifiers. In this project, the operational amplifiers themselves are designed according to Baker. [6] It is a two-stage operational amplifier with miller com- pensation. It has a differential amplifier on the input and a common-source amplifier at the output. Furthermore, it has a common mode feedback circuit and an out- put buffer. For the 1-bit quantization of the signal, a clocked com- parator with RS-latch is used. The comparator is also fully differential. It is only active if the clock signal is high and it then sets the inputs for theRS-latch, which is implemented with NAND gates. This latch provides the pulse density modulated output y of the modulator. Transmission gates are used to implement the function of the switches in the design proposal. [3] A transmission gate consists of a PMOS and a NMOS transistor pair. As the supply voltage is larger than the sumof the two threshold voltages in the 180 nm technology, the complementary switch is still effective. To turn on both transistors, it needs a high and an inverted low clock signal, and 28 instances are used in total. IMPLEMENTATION OF THE CO-SIMULATION AND TEST To simulate the full-schematic model from Simulink, the co-simulation interface between the two environ- ments is required. For this purpose, a coupler block is inserted both into the Simulink and into the Cadence model. [7] Figure 6 shows the integrated model in Simulink. The coupler block has two inputs and two outputs. On the left, the input side, the positive and negative portion of the sinusoid signal are processed to Cadence Virtuoso and the simulator Spectre, respectively. The separation into positive and negative signal parts is Fig. 6 Implementation of the co-simulation in Simulink. Fig. 5 Spectrumcomparisonof themodel of theΔΣ-toolbox (blue) and the Simsides model (red). Table 1 Capacitor values for the ΔΣ modulator Name Description Value CS Sampling capacitor first stage 128fF CI1 Integration capacitor first stage 595fF Cs1 Sampling capacitor second stage, first branch 46fF Cs2 Sampling capacitor second stage, second branch 128fF CI2 Integration capacitor second stage 915fF